Lines Matching +full:0 +full:x108000
14 #define HCLGE_CMDQ_RX_INVLD_B 0
26 #define HCLGE_TQP_REG_OFFSET 0x80000
27 #define HCLGE_TQP_REG_SIZE 0x200
30 #define HCLGE_TQP_EXT_REG_OFFSET 0x100
33 #define HCLGE_RCB_INIT_FLAG_EN_B 0
43 #define HCLGE_TQP_MAP_TYPE_PF 0
45 #define HCLGE_TQP_MAP_TYPE_B 0
61 #define HCLGE_VECTOR_ID_L_S 0
62 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)
65 #define HCLGE_INT_TYPE_S 0
66 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
153 #define HCLGE_PF_STATE_DONE_B 0
157 #define HCLGE_PF_MAC_NUM_MASK 0x3
186 #define HCLGE_CFG_OFFSET_S 0
187 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
197 #define HCLGE_CFG_PHY_ADDR_S 0
198 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
203 #define HCLGE_CFG_MAC_ADDR_H_S 0
204 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
209 #define HCLGE_CFG_SPEED_ABILITY_S 0
210 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
217 #define HCLGE_CFG_PF_RSS_SIZE_S 0
218 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)
230 #define HCLGE_MAC_MODE 0x0
231 #define HCLGE_DESC_NUM 0x40
233 #define HCLGE_ALLOC_VALID_B 0
244 #define HCLGE_RSS_TC_OFFSET_S 0
245 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)
252 #define HCLGE_LINK_STATUS_UP_B 0
308 #define HCLGE_PF_RST_ALL_VF_RDY_B 0
313 #define HCLGE_CFG_SPEED_S 0
314 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
322 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
329 #define HCLGE_TQP_ENABLE_B 0
331 #define HCLGE_MAC_CFG_AN_EN_B 0
346 u8 query_type; /* 0: sfp speed, 1: active speed */
357 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
360 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
363 #define HCLGE_MAC_FEC_OFF 0
387 #define HCLGE_MAC_UPLINK_PORT 0x100
407 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
413 #define HCLGE_MAC_EPORT_PFID_S 0
414 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
429 #define HCLGE_UMV_SPC_ALC_B 0
437 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
488 #define HCLGE_INGRESS_BYPASS_B 0
496 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
500 #define HCLGE_SWITCH_NO_MASK 0x0
501 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
502 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
503 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
504 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
517 HCLGE_MAC_VLAN_NIC_SEL = 0,
521 #define HCLGE_ACCEPT_TAG1_B 0
541 #define HCLGE_REM_TAG1_EN_B 0
603 #define HCLGE_TSO_MSS_MIN_S 0
604 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
615 #define HCLGE_GRO_EN_B 0
624 #define HCLGE_TQP_RESET_B 0
646 #define HCLGE_PF_RESET_DONE_BIT BIT(0)
653 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
656 #define HCLGE_CMD_COMMON_LB_DONE_B BIT(0)
665 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
666 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
667 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
668 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
669 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
671 #define HCLGE_LED_LOCATE_STATE_S 0
672 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
707 #define HCLGE_FD_EPORT_SW_EN_B 0
728 #define HCLGE_FD_AD_DROP_B 0
738 #define HCLGE_FD_AD_WR_RULE_ID_B 0
761 #define HCLGE_FD_USER_DEF_OFT_S 0
762 #define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)
820 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U