1 /* SPDX-License-Identifier: GPL-2.0 */
4  * Copyright (C) 2017-2025 Microchip Technology Inc.
13 #include <linux/pcs/pcs-xpcs.h>
18 #include <linux/platform_data/microchip-ksz.h>
133 	u32 fiber:1;			/* port is fiber */  member
362 	 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus
371 	 * and setting up access permissions for the selected mode.
374 	 *  - 0 on success.
375 	 *  - Negative error code on failure.
380 	 * @create_phy_addr_map: Function pointer to create a port-to-PHY
387 	 * addresses according to the configured access mode (SPI or side MDIO)
393 	 *  - 0 on success.
394 	 *  - Negative error code on failure (e.g., invalid configuration).
439 				    unsigned int mode,
477 	return dev->regmap[KSZ_REGMAP_8];  in ksz_regmap_8()
482 	return dev->regmap[KSZ_REGMAP_16];  in ksz_regmap_16()
487 	return dev->regmap[KSZ_REGMAP_32];  in ksz_regmap_32()
492 	return dev->chip_id == KSZ8463_CHIP_ID;  in ksz_is_ksz8463()
501 		dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,  in ksz_read8()
514 		dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,  in ksz_read16()
527 		dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,  in ksz_read32()
541 		dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,  in ksz_read64()
555 		dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,  in ksz_write8()
567 		dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,  in ksz_write16()
579 		dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,  in ksz_write32()
592 		dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,  in ksz_rmw16()
605 		dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,  in ksz_rmw32()
629 		dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,  in ksz_rmw8()
638 	return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pread8()
644 	return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pread16()
650 	return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pread32()
656 	return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);  in ksz_pwrite8()
662 	return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_pwrite16()
669 	return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_pwrite32()
676 	return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_prmw8()
683 	return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),  in ksz_prmw32()
701 	return dev->chip_id == KSZ8795_CHIP_ID ||  in ksz_is_ksz87xx()
702 	       dev->chip_id == KSZ8794_CHIP_ID ||  in ksz_is_ksz87xx()
703 	       dev->chip_id == KSZ8765_CHIP_ID;  in ksz_is_ksz87xx()
708 	return dev->chip_id == KSZ88X3_CHIP_ID;  in ksz_is_ksz88x3()
713 	return dev->chip_id == KSZ8895_CHIP_ID ||  in ksz_is_8895_family()
714 	       dev->chip_id == KSZ8864_CHIP_ID;  in ksz_is_8895_family()
731 	return dev->chip_id == KSZ9477_CHIP_ID;  in is_ksz9477()
736 	return dev->chip_id == LAN9370_CHIP_ID ||  in is_lan937x()
737 		dev->chip_id == LAN9371_CHIP_ID ||  in is_lan937x()
738 		dev->chip_id == LAN9372_CHIP_ID ||  in is_lan937x()
739 		dev->chip_id == LAN9373_CHIP_ID ||  in is_lan937x()
740 		dev->chip_id == LAN9374_CHIP_ID;  in is_lan937x()
745 	return (dev->chip_id == LAN9371_CHIP_ID ||  in is_lan937x_tx_phy()
746 		dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4;  in is_lan937x_tx_phy()
751 	return dev->info->sgmii_port - 1;  in ksz_get_sgmii_port()
756 	return dev->info->sgmii_port > 0;  in ksz_has_sgmii_port()
761 	return dev->info->sgmii_port == port + 1;  in ksz_is_sgmii_port()
823 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */
870 /* TXQ Split Control Register for per-port, per-queue configuration.
872  * Register offset formula: 0xAF + (port * 4) + (3 - queue)
876 	(0xAF + ((port) * 4) + (3 - (queue)))
879  *   0 = Strict priority mode (highest-priority queue first)
880  *   1 = Weighted Fair Queuing (WFQ) mode:
931 		.max_register = BIT(regbits) - 1,			\
961 		.max_register = BIT(regbits) - 1,			\