Lines Matching full:dll
185 /* PHY DLL control settings */
187 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */
188 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */
190 /* PHY DLL configuration register 1 */
193 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
194 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */
196 /* PHY DLL configuration register 2 */
198 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */
200 /* PHY DLL master and slave delay line configuration settings */
205 /* PHY DLL offset setting register */
207 /* DLL LBT setting register */
209 /* DLL Status register */
211 #define DLL_LOCK_STS BIT(0)/* DLL is locked and ready */
213 * Captures the value of DLL's lock error status information. Value is valid
463 /* enable phy dll */ in dwcmshc_phy_init()
743 * Disable DLL and reset both of sample and drive clock. in dwcmshc_rk3568_set_clock()
744 * The bypass bit and start bit need to be set if DLL is not locked. in dwcmshc_rk3568_set_clock()
762 /* Reset DLL */ in dwcmshc_rk3568_set_clock()
776 /* Init DLL settings */ in dwcmshc_rk3568_set_clock()
785 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); in dwcmshc_rk3568_set_clock()
890 * cannot use DLL for this condition. in dwcmshc_rk35xx_postinit()
1537 /* here need make dll locked when in hs400 at 200MHz */ in sdhci_eic7700_set_uhs_signaling()
1546 0x3, PHY_DLL_CNFG1_R);/* DLL wait cycle input */ in sdhci_eic7700_set_uhs_signaling()
1547 /* DLL jump step input */ in sdhci_eic7700_set_uhs_signaling()
1551 /* Sets the value of DLL's offset input */ in sdhci_eic7700_set_uhs_signaling()
1554 * Sets the value of DLL's olbt loadval input. Controls the Ibt in sdhci_eic7700_set_uhs_signaling()
1555 * timer's timeout value at which DLL runs a revalidation cycle. in sdhci_eic7700_set_uhs_signaling()
1564 pr_err("%s: DLL lock timeout! status: 0x%x\n", in sdhci_eic7700_set_uhs_signaling()
1571 pr_err("%s: DLL lock failed!err_status:0x%x\n", in sdhci_eic7700_set_uhs_signaling()