Lines Matching full:timings
125 * @timings_arr_size: number of 'timings' elements
129 * @timings: DDR memory timings, from device tree
131 * @bypass_timing_row: value for timing row register for bypass timings
132 * @bypass_timing_data: value for timing data register for bypass timings
134 * timings
170 const struct lpddr3_timings *timings;
302 * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
379 * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
382 * Low-level function for changing timings for DRAM memory clocking from
406 * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
410 * Low-level function for changing timings for DRAM memory operating from main
412 * frequency must have corresponding timings register values in order to keep
500 * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
504 * Function changes the DRAM timings for the temporary 'bypass' mode.
526 * This mode is used only temporary but if required, changes voltage and timings
575 * timings: set 0 and set 1. The set 0 is used when main clock source is
609 * We are safe to increase the timings for current bypass frequency.
1033 * The function calculates timings and creates a register value ready for
1034 * a frequency transition. The register contains a few timings. They are
1052 val = dmc->timings->tRFC / clk_period_ps;
1053 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1058 val = dmc->timings->tRRD / clk_period_ps;
1059 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1064 val = dmc->timings->tRPab / clk_period_ps;
1065 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1070 val = dmc->timings->tRCD / clk_period_ps;
1071 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
1076 val = dmc->timings->tRC / clk_period_ps;
1077 val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
1082 val = dmc->timings->tRAS / clk_period_ps;
1083 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
1088 /* data related timings */
1089 val = dmc->timings->tWTR / clk_period_ps;
1090 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
1095 val = dmc->timings->tWR / clk_period_ps;
1096 val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
1101 val = dmc->timings->tRTP / clk_period_ps;
1102 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
1107 val = dmc->timings->tW2W_C2C / clk_period_ps;
1108 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
1113 val = dmc->timings->tR2R_C2C / clk_period_ps;
1114 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
1119 val = dmc->timings->tWL / clk_period_ps;
1120 val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
1125 val = dmc->timings->tDQSCK / clk_period_ps;
1126 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
1131 val = dmc->timings->tRL / clk_period_ps;
1132 val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
1137 /* power related timings */
1138 val = dmc->timings->tFAW / clk_period_ps;
1139 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
1144 val = dmc->timings->tXSR / clk_period_ps;
1145 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
1150 val = dmc->timings->tXP / clk_period_ps;
1151 val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
1156 val = dmc->timings->tCKE / clk_period_ps;
1157 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
1162 val = dmc->timings->tMRD / clk_period_ps;
1163 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
1206 dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dev,
1209 if (!dmc->timings) {
1210 dev_warn(dev, "could not get timings from DT\n");
1232 /* Take the highest frequency's timings as 'bypass' */
1409 * memory parameters: timings for each operating frequency.
1460 dev_warn(dev, "couldn't initialize timings settings\n");