Lines Matching +full:2 +full:nd +full:- +full:cell
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
22 #define TW5864_EMU_EN_SEN BIT(2)
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
79 #define TW5864_VLC_BUF_ID (7 << 2)
86 * 0 2 falf D1 in 1 MB
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
201 #define TW5864_DI_EN BIT(2)
203 * De-interlacer Mode
205 * 0 Normal Un-Shuffled Frame
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
255 #define TW5864_ME_EN BIT(2)
260 /* Search Option (Default 2"b01) */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
341 (0x0c00 | (channel << 4) | (frame << 2))
358 #define TW5864_FRAME BIT(2)
362 * 2 2D1 in bus n
366 /* Bus 2 goes in TW5864_FRAME_BUS1 in [12:8] */
380 * 0x2cf: 2 D1
384 * 0x2cf: 2 D1
388 * 0x23f: 2 D1 (PAL)
391 * 0x1df: 2 D1 (NTSC)
395 * 0x23f: 2 D1 (PAL)
398 * 0x1df: 2 D1 (NTSC)
422 * Swap byte order of VLC stream in d-word.
470 #define TW5864_VLC_END_SLICE BIT(2)
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
520 #define TW5864_ADPCM_ENC BIT(2)
568 * Bit[2:0] ch0
660 /* [2:0] Data valid signal width by system clock cycles */
679 * 2 Two system clock delay
691 * 2'b00 phase set to 180 degree
692 * 2'b01 phase set to 270 degree
693 * 2'b10 phase set to 0 degree
694 * 2'b11 phase set to 90 degree
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
712 /* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */
720 * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL
725 #define TW5864_SYSPLL_P_SHIFT 2
726 #define TW5864_SYSPLL_P (0x03 << 2)
737 * 2 9 uA
748 * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL,
761 #define TW5864_SYSPLL_LP_X8_SHIFT 2
766 * 2 2.2K ohms
769 #define TW5864_SYSPLL_LP_X8 (0x03 << 2)
774 * 01 x1/2
813 #define TW5864_SYSPLL_CFG BIT(2)
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
864 * Bit[2]: MV DSP interrupt
868 * Bit[6]: gpio 2 interrupt
882 * Bit[2]: Reserved
898 #define TW5864_INTR_MV_DSP BIT(2)
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
928 * 1 Downscale Y to 1/2
942 * 1 Max 2 channels
969 * 11 D1 with 1/2 size in X (for CIF frame)
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1015 * [2:0] Data valid counter after read command to DDR. This is the delay value
1045 * [2:0] CAS latency, the delay cycle between internal read command and the
1058 * 2 1G DDR on board
1059 * DDR_ON_CHIP_MAP [2]
1068 * 1 DDR self-test mode
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1080 #define TW5864_WRITE_FLAG BIT(2)
1085 * 2 write 32'hha5a55a5a to DDR
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1125 #define TW5864_AUD_DEC_REQ0_ENB BIT(2)
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1158 * (2) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1162 * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1"
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1214 #define TW5864_MV_EOF BIT(2)
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1387 * 1 2ms
1388 * 2 4ms
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1410 #define TW5864_BRST_LENGTH_SHIFT 2
1411 /* Length of 32-bit data burst */
1412 #define TW5864_BRST_LENGTH (0x3fff << 2)
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505 * 0 = Non-standard signal
1506 * Read-only
1510 * 1 = Non-interlaced signal
1512 * Read-only
1535 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI_SHIFT 2
1536 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI (0x03 << 2)
1558 /* HUE These bits control the color hue as 2's complement number. They have
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1630 #define TW5864_INDIR_VIN_D_MCVSN BIT(2)
1636 * 1 Type 2 color stripe protection
1641 /* Read-only */
1645 * Read-only.
1654 * 2 SECAM
1674 * 2 SECAM
1687 * process. This bit is a self-clearing bit
1700 #define TW5864_INDIR_VIN_F_SECAMEN BIT(2)
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1721 * 2 0.38
1738 /* [3:0] channel 2, [7:4] channel 3 */
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1749 * 2 u-Law output
1750 * 3 A-Law output
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1803 * 2 32kHz setting
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1845 #define TW5864_INDIR_AIN_0x0E4_ADATPDLY BIT(2)
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1850 * 2 u-Law input
1851 * 3 A-Law input
1865 * [2:0]: REV_ID The revision number is 0h
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1914 * bit 2: interrupt occurs in 0x2d2 & 0x2da
1948 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN BIT(2)
1950 * Define the threshold of cell for blind detection.
1987 * 2 Detecting motion for any field
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2016 * 1 2 field intervals
2088 * [9:0] The motion cell count of a specific channel selected by 0x382. This is
2092 /* The motion detection cell sensitivity for DI purpose */
2129 #define TW5864_INDIR_CLK0_SEL_PV_SHIFT 2
2130 #define TW5864_INDIR_CLK0_SEL_PV_MASK (0x3 << 2)