Lines Matching +full:multi +full:- +full:protocol

2   Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
36 * Data access protocol: Fast Access Sequential Interface (fasi)
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error  At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER  modes:
113 *  + multi master mode means use of repeated starts
118 * Single/multi master selected via the flags in the FASI protocol.
121 *  Default is single master, DAP FASI changes multi-master setting silently
134 * Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and
143 * If ten-bit I2C device addresses are used, the minimum chunk size must be six,
153 * <S> <devR> --- <P>
155 * In multi-master mode, the data must immediately follow the address (an I2C
158 * 10-bit I2C device addresses are used).
160 * The 7-bit or 10-bit i2c address parameters is a runtime parameter.
163 *-------------------------------------------------------------------------------
167 *       +----------------+----------------+
169 *       +----------------+----------------+
170 *       | single | multi | single | multi |
171 * ------+--------+-------+--------+-------+
174 * ------+--------+-------+--------+-------+
204 #error  DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode
212 #error  DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode
235 /*-------- Public API functions ----------------------------------------------*/
242 #define DRXDAP_FASI_SMM_SWITCH    0x40000000	/* single/multi master switch */