Lines Matching +full:0 +full:xa010
217 for (i = 0; i < 64; i += 4) {
218 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
220 readl((u32 __iomem *)hvs->dlist + i + 0),
238 return 0;
253 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) {
263 next_entry_start = 0;
267 drm_printf(&p, "dlist: %02d: 0x%08x\n", j,
280 return 0;
294 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) {
310 next_entry_start = 0;
316 drm_printf(&p, "dlist: %02d: 0x%08x\n", j,
329 return 0;
350 return 0;
356 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
358 ((((c0) & 0x1ff) << 0) | \
359 (((c1) & 0x1ff) << 9) | \
360 (((c2) & 0x1ff) << 18))
362 /* The whole filter kernel is arranged as the coefficients 0-16 going
375 VC4_PPF_FILTER_WORD(c15, c15, 0)}
384 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
408 for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
417 return 0;
446 for (i = 0; i < crtc->gamma_size; i++)
448 for (i = 0; i < crtc->gamma_size; i++)
450 for (i = 0; i < crtc->gamma_size; i++)
465 for (i = 0; i < length; i++) {
478 u8 field = 0;
484 return 0;
494 case 0:
510 case 0:
554 case 0:
555 return 0;
563 if (ret == 0)
566 return 0;
599 case 0:
600 return 0;
637 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
639 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
654 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
661 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
671 ((vc4->gen == VC4_GEN_4) ? SCALER_DISPBKGND_GAMMA : 0) |
672 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
681 return 0;
705 disp_ctrl1 | (interlace ? SCALER6_DISPX_CTRL1_INTLACE : 0));
711 (oneshot ? SCALER6_DISPX_CTRL0_ONESHOT : 0) |
717 return 0;
735 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
799 u32 dlist_count = 0;
832 return 0;
867 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
943 unsigned int zpos = 0;
1138 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
1154 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
1186 return 0;
1236 for (i = 0; i < VC4_NUM_UPM_HANDLES; i++) {
1237 refcount_set(&hvs->upm_refcounts[i].refcount, 0);
1283 drm_mm_init(&hvs->lbm_mm, 0, lbm_size);
1295 drm_mm_init(&hvs->upm_mm, 0, 1024 * HVS_UBM_WORD_SIZE);
1316 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
1334 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
1342 SCALER_DISPCTRL_DSPEIEOF(0) |
1345 SCALER_DISPCTRL_DSPEIEOLN(0) |
1348 SCALER_DISPCTRL_DSPEISLUR(0) |
1355 SCALER5_DISPCTRL_DSPEIEOF(0) |
1358 SCALER5_DISPCTRL_DSPEIEOLN(0) |
1361 SCALER5_DISPCTRL_DSPEISLUR(0) |
1391 return 0;
1394 #define CFC1_N_NL_CSC_CTRL(x) (0xa000 + ((x) * 0x3000))
1395 #define CFC1_N_MA_CSC_COEFF_C00(x) (0xa008 + ((x) * 0x3000))
1396 #define CFC1_N_MA_CSC_COEFF_C01(x) (0xa00c + ((x) * 0x3000))
1397 #define CFC1_N_MA_CSC_COEFF_C02(x) (0xa010 + ((x) * 0x3000))
1398 #define CFC1_N_MA_CSC_COEFF_C03(x) (0xa014 + ((x) * 0x3000))
1399 #define CFC1_N_MA_CSC_COEFF_C04(x) (0xa018 + ((x) * 0x3000))
1400 #define CFC1_N_MA_CSC_COEFF_C10(x) (0xa01c + ((x) * 0x3000))
1401 #define CFC1_N_MA_CSC_COEFF_C11(x) (0xa020 + ((x) * 0x3000))
1402 #define CFC1_N_MA_CSC_COEFF_C12(x) (0xa024 + ((x) * 0x3000))
1403 #define CFC1_N_MA_CSC_COEFF_C13(x) (0xa028 + ((x) * 0x3000))
1404 #define CFC1_N_MA_CSC_COEFF_C14(x) (0xa02c + ((x) * 0x3000))
1405 #define CFC1_N_MA_CSC_COEFF_C20(x) (0xa030 + ((x) * 0x3000))
1406 #define CFC1_N_MA_CSC_COEFF_C21(x) (0xa034 + ((x) * 0x3000))
1407 #define CFC1_N_MA_CSC_COEFF_C22(x) (0xa038 + ((x) * 0x3000))
1408 #define CFC1_N_MA_CSC_COEFF_C23(x) (0xa03c + ((x) * 0x3000))
1409 #define CFC1_N_MA_CSC_COEFF_C24(x) (0xa040 + ((x) * 0x3000))
1411 #define SCALER_PI_CMP_CSC_RED0(x) (0x200 + ((x) * 0x40))
1412 #define SCALER_PI_CMP_CSC_RED1(x) (0x204 + ((x) * 0x40))
1413 #define SCALER_PI_CMP_CSC_RED_CLAMP(x) (0x208 + ((x) * 0x40))
1414 #define SCALER_PI_CMP_CSC_CFG(x) (0x20c + ((x) * 0x40))
1415 #define SCALER_PI_CMP_CSC_GREEN0(x) (0x210 + ((x) * 0x40))
1416 #define SCALER_PI_CMP_CSC_GREEN1(x) (0x214 + ((x) * 0x40))
1417 #define SCALER_PI_CMP_CSC_GREEN_CLAMP(x) (0x218 + ((x) * 0x40))
1418 #define SCALER_PI_CMP_CSC_BLUE0(x) (0x220 + ((x) * 0x40))
1419 #define SCALER_PI_CMP_CSC_BLUE1(x) (0x224 + ((x) * 0x40))
1420 #define SCALER_PI_CMP_CSC_BLUE_CLAMP(x) (0x228 + ((x) * 0x40))
1433 { 0x004A8542, 0x0, 0x0066254A, 0x0, 0xFF908A0D },
1434 { 0x004A8542, 0xFFE6ED5D, 0xFFCBF856, 0x0, 0x0043C9A3 },
1435 { 0x004A8542, 0x00811A54, 0x0, 0x0, 0xFF759502 }
1440 { 0x004A8542, 0x0, 0x0072BC44, 0x0, 0xFF83F312 },
1441 { 0x004A8542, 0xFFF25A22, 0xFFDDE4D0, 0x0, 0x00267064 },
1442 { 0x004A8542, 0x00873197, 0x0, 0x0, 0xFF6F7DC0 }
1447 { 0x004A8542, 0x0, 0x006B4A17, 0x0, 0xFF8B653F },
1448 { 0x004A8542, 0xFFF402D9, 0xFFDDE4D0, 0x0, 0x0024C7AE },
1449 { 0x004A8542, 0x008912CC, 0x0, 0x0, 0xFF6D9C8B }
1456 { 0x00400000, 0x0, 0x0059BA5E, 0x0, 0xFFA645A1 },
1457 { 0x00400000, 0xFFE9F9AC, 0xFFD24B97, 0x0, 0x0043BABB },
1458 { 0x00400000, 0x00716872, 0x0, 0x0, 0xFF8E978D }
1463 { 0x00400000, 0x0, 0x0064C985, 0x0, 0xFF9B367A },
1464 { 0x00400000, 0xFFF402E1, 0xFFE20A40, 0x0, 0x0029F2DE },
1465 { 0x00400000, 0x0076C226, 0x0, 0x0, 0xFF893DD9 }
1470 { 0x00400000, 0x0, 0x005E3F14, 0x0, 0xFFA1C0EB },
1471 { 0x00400000, 0xFFF577F6, 0xFFDB580F, 0x0, 0x002F2FFA },
1472 { 0x00400000, 0x007868DB, 0x0, 0x0, 0xFF879724 }
1489 HVS_WRITE(SCALER6(PRI_MAP0), 0xffffffff);
1490 HVS_WRITE(SCALER6(PRI_MAP1), 0xffffffff);
1493 for (i = 0; i < 6; i++) {
1496 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]);
1497 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);
1498 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]);
1499 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]);
1500 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]);
1502 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);
1508 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]);
1517 for (i = 0; i < 8; i++) {
1518 HVS_WRITE(SCALER_PI_CMP_CSC_RED0(i), 0x1f002566);
1519 HVS_WRITE(SCALER_PI_CMP_CSC_RED1(i), 0x3994);
1520 HVS_WRITE(SCALER_PI_CMP_CSC_RED_CLAMP(i), 0xfff00000);
1521 HVS_WRITE(SCALER_PI_CMP_CSC_CFG(i), 0x1);
1522 HVS_WRITE(SCALER_PI_CMP_CSC_GREEN0(i), 0x18002566);
1523 HVS_WRITE(SCALER_PI_CMP_CSC_GREEN1(i), 0xf927eee2);
1524 HVS_WRITE(SCALER_PI_CMP_CSC_GREEN_CLAMP(i), 0xfff00000);
1525 HVS_WRITE(SCALER_PI_CMP_CSC_BLUE0(i), 0x18002566);
1526 HVS_WRITE(SCALER_PI_CMP_CSC_BLUE1(i), 0x43d80000);
1527 HVS_WRITE(SCALER_PI_CMP_CSC_BLUE_CLAMP(i), 0xfff00000);
1531 return 0;
1551 * channel 0.
1556 reg = 0;
1577 * lines. to channel 0.
1582 reg = 0;
1602 base = 0;
1619 HVS_WRITE(SCALER6_DISPX_COB(0),
1628 return 0;
1640 regs = vc4_ioremap_regs(pdev, 0);
1743 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1744 vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
1749 return 0;