Lines Matching full:dsi
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
550 /* General DSI hardware state. */
571 /* DSI channel for the panel we're connected to. */
578 /* Input clock from CPRMAN to the digital PHY, for the DSI
583 /* Input clock to the analog PHY, used to generate the DSI bit
588 /* HS Clocks generated within the DSI analog PHY. */
614 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
616 struct drm_device *drm = dsi->bridge.dev;
617 struct dma_chan *chan = dsi->reg_dma_chan;
626 writel(val, dsi->regs + offset);
630 *dsi->reg_dma_mem = val;
633 dsi->reg_paddr + offset,
634 dsi->reg_dma_paddr,
655 readl(dsi->regs + (offset)); \
658 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
660 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
662 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
663 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
715 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
728 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
730 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
733 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
734 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
735 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
738 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
739 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
740 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
743 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
744 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
745 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
757 dev_warn(&dsi->pdev->dev,
758 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
761 vc4_dsi_latch_ulps(dsi, false);
765 /* The DSI module can't be disabled while the module is
770 vc4_dsi_latch_ulps(dsi, ulps);
776 dev_warn(&dsi->pdev->dev,
777 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
805 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
816 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
817 struct device *dev = &dsi->pdev->dev;
819 clk_disable_unprepare(dsi->pll_phy_clock);
820 clk_disable_unprepare(dsi->escape_clock);
821 clk_disable_unprepare(dsi->pixel_clock);
827 * DSI PLL divider.
831 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
832 * the pixel clock), only has an integer divider off of DSI.
843 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
844 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
847 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
862 pixel_clock_hz = pll_clock / dsi->divider;
879 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
881 struct device *dev = &dsi->pdev->dev;
897 drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
902 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
903 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
904 drm_print_regset32(&p, &dsi->regset);
923 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
924 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
926 dev_err(&dsi->pdev->dev,
930 /* Reset the DSI and all its fifos. */
943 if (dsi->variant->port == 0) {
947 if (dsi->lanes < 2)
950 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
971 if (dsi->lanes < 4)
973 if (dsi->lanes < 3)
975 if (dsi->lanes < 2)
988 ret = clk_prepare_enable(dsi->escape_clock);
990 drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n",
995 ret = clk_prepare_enable(dsi->pll_phy_clock);
997 drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret);
1001 hs_clock = clk_get_rate(dsi->pll_phy_clock);
1008 * pixel clock for pushing pixels into DSI.
1011 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
1017 ret = clk_prepare_enable(dsi->pixel_clock);
1019 drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret);
1023 /* How many ns one DSI unit interval is. Note that the clock
1087 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1088 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1089 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1091 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1093 (dsi->variant->port == 0 ?
1119 if (dsi->variant->port == 0)
1129 vc4_dsi_ulps(dsi, false);
1131 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1133 VC4_SET_FIELD(dsi->divider,
1135 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1148 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1157 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1158 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1159 drm_print_regset32(&p, &dsi->regset);
1166 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1168 /* Attach the panel or bridge to the dsi bridge */
1169 return drm_bridge_attach(bridge->encoder, dsi->out_bridge,
1170 &dsi->bridge, flags);
1176 struct vc4_dsi *dsi = host_to_dsi(host);
1177 struct drm_device *drm = dsi->bridge.dev;
1255 dsi->xfer_result = 0;
1256 reinit_completion(&dsi->xfer_completion);
1257 if (dsi->variant->port == 0) {
1285 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1287 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1288 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1292 ret = dsi->xfer_result;
1309 drm_err(drm, "DSI returned %db, expecting %db\n",
1332 drm_err(drm, "DSI transfer failed, resetting: %d\n", ret);
1349 struct vc4_dsi *dsi = host_to_dsi(host);
1352 dsi->lanes = device->lanes;
1353 dsi->channel = device->channel;
1354 dsi->mode_flags = device->mode_flags;
1358 dsi->format = DSI_PFORMAT_RGB888;
1359 dsi->divider = 24 / dsi->lanes;
1362 dsi->format = DSI_PFORMAT_RGB666;
1363 dsi->divider = 24 / dsi->lanes;
1366 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1367 dsi->divider = 18 / dsi->lanes;
1370 dsi->format = DSI_PFORMAT_RGB565;
1371 dsi->divider = 16 / dsi->lanes;
1374 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1375 dsi->format);
1379 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1380 dev_err(&dsi->pdev->dev,
1385 drm_bridge_add(&dsi->bridge);
1387 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1389 drm_bridge_remove(&dsi->bridge);
1399 struct vc4_dsi *dsi = host_to_dsi(host);
1401 component_del(&dsi->pdev->dev, &vc4_dsi_ops);
1402 drm_bridge_remove(&dsi->bridge);
1427 struct vc4_dsi *dsi = to_vc4_dsi(encoder);
1429 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset);
1467 static void dsi_handle_error(struct vc4_dsi *dsi,
1474 drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port,
1487 struct vc4_dsi *dsi = data;
1502 struct vc4_dsi *dsi = data;
1508 dsi_handle_error(dsi, &ret, stat,
1510 dsi_handle_error(dsi, &ret, stat,
1512 dsi_handle_error(dsi, &ret, stat,
1514 dsi_handle_error(dsi, &ret, stat,
1516 dsi_handle_error(dsi, &ret, stat,
1518 dsi_handle_error(dsi, &ret, stat,
1520 dsi_handle_error(dsi, &ret, stat,
1522 dsi_handle_error(dsi, &ret, stat,
1525 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1528 complete(&dsi->xfer_completion);
1531 complete(&dsi->xfer_completion);
1532 dsi->xfer_result = -ETIMEDOUT;
1542 * @dsi: DSI encoder
1545 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1547 struct device *dev = &dsi->pdev->dev;
1548 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1559 dsi->clk_onecell = devm_kzalloc(dev,
1560 sizeof(*dsi->clk_onecell) +
1564 if (!dsi->clk_onecell)
1566 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1569 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1575 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1582 * setting both our parent DSI PLL's rate and this
1600 dsi->clk_onecell->hws[i] = &fix->hw;
1605 dsi->clk_onecell);
1610 struct vc4_dsi *dsi = ptr;
1611 struct device *dev = &dsi->pdev->dev;
1613 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr);
1614 dsi->reg_dma_mem = NULL;
1619 struct vc4_dsi *dsi = ptr;
1621 dma_release_channel(dsi->reg_dma_chan);
1622 dsi->reg_dma_chan = NULL;
1627 struct vc4_dsi *dsi =
1630 kfree(dsi);
1633 static void vc4_dsi_get(struct vc4_dsi *dsi)
1635 kref_get(&dsi->kref);
1638 static void vc4_dsi_put(struct vc4_dsi *dsi)
1640 kref_put(&dsi->kref, &vc4_dsi_release);
1645 struct vc4_dsi *dsi = ptr;
1647 vc4_dsi_put(dsi);
1654 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1655 struct drm_encoder *encoder = &dsi->encoder.base;
1658 vc4_dsi_get(dsi);
1660 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi);
1664 dsi->variant = of_device_get_match_data(dev);
1666 dsi->encoder.type = dsi->variant->port ?
1669 dsi->regs = vc4_ioremap_regs(pdev, 0);
1670 if (IS_ERR(dsi->regs))
1671 return PTR_ERR(dsi->regs);
1673 dsi->regset.base = dsi->regs;
1674 dsi->regset.regs = dsi->variant->regs;
1675 dsi->regset.nregs = dsi->variant->nregs;
1687 if (dsi->variant->broken_axi_workaround) {
1690 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1691 &dsi->reg_dma_paddr,
1693 if (!dsi->reg_dma_mem) {
1698 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi);
1705 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1706 if (IS_ERR(dsi->reg_dma_chan)) {
1707 ret = PTR_ERR(dsi->reg_dma_chan);
1714 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi);
1722 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1726 init_completion(&dsi->xfer_completion);
1732 if (dsi->reg_dma_mem)
1737 "vc4 dsi", dsi);
1740 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1747 dsi->escape_clock = devm_clk_get(dev, "escape");
1748 if (IS_ERR(dsi->escape_clock)) {
1749 ret = PTR_ERR(dsi->escape_clock);
1755 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1756 if (IS_ERR(dsi->pll_phy_clock)) {
1757 ret = PTR_ERR(dsi->pll_phy_clock);
1763 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1764 if (IS_ERR(dsi->pixel_clock)) {
1765 ret = PTR_ERR(dsi->pixel_clock);
1771 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0);
1772 if (IS_ERR(dsi->out_bridge))
1773 return PTR_ERR(dsi->out_bridge);
1776 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1782 ret = vc4_dsi_init_phy_clocks(dsi);
1797 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1811 struct vc4_dsi *dsi;
1813 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1814 if (!dsi)
1816 dev_set_drvdata(dev, dsi);
1818 kref_init(&dsi->kref);
1820 dsi->pdev = pdev;
1821 dsi->bridge.funcs = &vc4_dsi_bridge_funcs;
1823 dsi->bridge.of_node = dev->of_node;
1825 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1826 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1827 dsi->dsi_host.dev = dev;
1828 mipi_dsi_host_register(&dsi->dsi_host);
1836 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1838 mipi_dsi_host_unregister(&dsi->dsi_host);
1839 vc4_dsi_put(dsi);