Lines Matching +full:hsic +full:- +full:state
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
137 /* Interrupt State, default value: 0x00 */
323 /* I2C Device Address re-assignment */
338 /* HSIC RX Control3, default value: 0x07 */
345 /* HSIC RX INT Registers */
417 /* HSIC TX CRTL, default value: 0x00 */
425 /* HSIC TX INT Low, default value: 0x00 */
428 /* HSIC TX INT High, default value: 0x00 */
431 /* HSIC Keeper, default value: 0x00 */
437 /* HSIC Flow Control General, default value: 0x02 */
442 /* HSIC Flow Control CTR13, default value: 0xfc */
445 /* HSIC Flow Control CTR14, default value: 0xff */
448 /* HSIC Flow Control CTR15, default value: 0xff */
451 /* HSIC Flow Control CTR50, default value: 0x03 */
454 /* HSIC Flow Control INTR0, default value: 0x00 */
648 /* E-MSC General Control, default value: 0x80 */
659 /* E-MSC Comma ErrorCNT, default value: 0x03 */
664 /* E-MSC RFIFO ByteCnt, default value: 0x00 */
678 /* E-MSC 1st Interrupt, default value: 0x00 */
689 /* E-MSC Interrupt Mask, default value: 0x00 */
692 /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
695 /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
698 /* E-MSC 2nd Interrupt, default value: 0x00 */
702 /* E-MSC Interrupt Mask, default value: 0x00 */
964 /* HSIC Div Ctl, default value: 0x05 */
1406 /* MDT State Machine Status, default value: 0x00 */