Lines Matching refs:lvds
1975 struct amdgpu_encoder_atom_dig *lvds = NULL;
1982 lvds =
1985 if (!lvds)
1988 lvds->native_mode.clock =
1990 lvds->native_mode.hdisplay =
1992 lvds->native_mode.vdisplay =
1994 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1996 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1998 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
2000 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
2002 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
2004 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
2006 lvds->panel_pwr_delay =
2008 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
2012 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2014 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2016 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
2018 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
2020 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
2022 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
2023 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
2026 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
2028 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
2030 encoder->native_mode = lvds->native_mode;
2033 lvds->linkb = true;
2035 lvds->linkb = false;
2089 lvds->native_mode.width_mm = panel_res_record->usHSize;
2090 lvds->native_mode.height_mm = panel_res_record->usVSize;
2103 return lvds;