Lines Matching +full:embedded +full:- +full:sync
1 // SPDX-License-Identifier: GPL-2.0
30 return (struct dpll_dump_ctx *)cb->ctx; in dpll_dump_context()
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
37 return -EMSGSIZE; in dpll_msg_add_dev_handle()
46 return -EMSGSIZE; in dpll_msg_add_dev_parent_handle()
56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) in dpll_pin_available()
58 xa_for_each(&pin->parent_refs, i, par_ref) in dpll_pin_available()
59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, in dpll_pin_available()
62 xa_for_each(&pin->dpll_refs, i, par_ref) in dpll_pin_available()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message
75 * * 0 - success
76 * * -EMSGSIZE - no space in message to attach pin handle
82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) in dpll_msg_add_pin_handle()
83 return -EMSGSIZE; in dpll_msg_add_pin_handle()
89 return rcu_dereference_rtnl(dev->dpll_pin); in dpll_netdev_pin()
93 * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev
117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
121 return -EMSGSIZE; in dpll_msg_add_mode()
138 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode_supported()
142 return -EMSGSIZE; in dpll_msg_add_mode_supported()
155 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { in dpll_msg_add_phase_offset_monitor()
156 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), in dpll_msg_add_phase_offset_monitor()
161 return -EMSGSIZE; in dpll_msg_add_phase_offset_monitor()
176 if (ops->phase_offset_avg_factor_get) { in dpll_msg_add_phase_offset_avg_factor()
177 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), in dpll_msg_add_phase_offset_avg_factor()
182 return -EMSGSIZE; in dpll_msg_add_phase_offset_avg_factor()
197 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, in dpll_msg_add_lock_status()
202 return -EMSGSIZE; in dpll_msg_add_lock_status()
207 return -EMSGSIZE; in dpll_msg_add_lock_status()
220 if (!ops->temp_get) in dpll_msg_add_temp()
222 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); in dpll_msg_add_temp()
226 return -EMSGSIZE; in dpll_msg_add_temp()
240 if (!ops->clock_quality_level_get) in dpll_msg_add_clock_quality_level()
242 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); in dpll_msg_add_clock_quality_level()
247 return -EMSGSIZE; in dpll_msg_add_clock_quality_level()
258 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_prio()
262 if (!ops->prio_get) in dpll_msg_add_pin_prio()
264 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_msg_add_pin_prio()
269 return -EMSGSIZE; in dpll_msg_add_pin_prio()
280 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_on_dpll_state()
284 if (!ops->state_on_dpll_get) in dpll_msg_add_pin_on_dpll_state()
286 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_pin_on_dpll_state()
291 return -EMSGSIZE; in dpll_msg_add_pin_on_dpll_state()
302 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_direction()
306 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_msg_add_pin_direction()
311 return -EMSGSIZE; in dpll_msg_add_pin_direction()
322 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_phase_adjust()
326 if (!ops->phase_adjust_get) in dpll_msg_add_pin_phase_adjust()
328 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_pin_phase_adjust()
334 return -EMSGSIZE; in dpll_msg_add_pin_phase_adjust()
345 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_phase_offset()
349 if (!ops->phase_offset_get) in dpll_msg_add_phase_offset()
351 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_phase_offset()
358 return -EMSGSIZE; in dpll_msg_add_phase_offset()
368 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_ffo()
372 if (!ops->ffo_get) in dpll_msg_add_ffo()
374 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_msg_add_ffo()
377 if (ret == -ENODATA) in dpll_msg_add_ffo()
389 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_freq()
394 if (!ops->frequency_get) in dpll_msg_add_pin_freq()
396 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_msg_add_pin_freq()
402 return -EMSGSIZE; in dpll_msg_add_pin_freq()
403 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { in dpll_msg_add_pin_freq()
406 return -EMSGSIZE; in dpll_msg_add_pin_freq()
407 freq = pin->prop.freq_supported[fs].min; in dpll_msg_add_pin_freq()
411 return -EMSGSIZE; in dpll_msg_add_pin_freq()
413 freq = pin->prop.freq_supported[fs].max; in dpll_msg_add_pin_freq()
417 return -EMSGSIZE; in dpll_msg_add_pin_freq()
430 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_esync()
435 if (!ops->esync_get) in dpll_msg_add_pin_esync()
437 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_msg_add_pin_esync()
439 if (ret == -EOPNOTSUPP) in dpll_msg_add_pin_esync()
445 return -EMSGSIZE; in dpll_msg_add_pin_esync()
447 return -EMSGSIZE; in dpll_msg_add_pin_esync()
452 return -EMSGSIZE; in dpll_msg_add_pin_esync()
467 return -EMSGSIZE; in dpll_msg_add_pin_esync()
476 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_ref_sync()
485 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { in dpll_msg_add_pin_ref_sync()
489 if (WARN_ON(!ops->ref_sync_get)) in dpll_msg_add_pin_ref_sync()
490 return -EOPNOTSUPP; in dpll_msg_add_pin_ref_sync()
491 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, in dpll_msg_add_pin_ref_sync()
497 return -EMSGSIZE; in dpll_msg_add_pin_ref_sync()
498 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) in dpll_msg_add_pin_ref_sync()
508 return -EMSGSIZE; in dpll_msg_add_pin_ref_sync()
515 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) in dpll_pin_is_freq_supported()
516 if (freq >= pin->prop.freq_supported[fs].min && in dpll_pin_is_freq_supported()
517 freq <= pin->prop.freq_supported[fs].max) in dpll_pin_is_freq_supported()
534 xa_for_each(&pin->parent_refs, index, ref) { in dpll_msg_add_pin_parents()
538 ppin = ref->pin; in dpll_msg_add_pin_parents()
539 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); in dpll_msg_add_pin_parents()
540 ret = ops->state_on_pin_get(pin, in dpll_msg_add_pin_parents()
547 return -EMSGSIZE; in dpll_msg_add_pin_parents()
548 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); in dpll_msg_add_pin_parents()
552 ret = -EMSGSIZE; in dpll_msg_add_pin_parents()
574 xa_for_each(&pin->dpll_refs, index, ref) { in dpll_msg_add_pin_dplls()
577 return -EMSGSIZE; in dpll_msg_add_pin_dplls()
578 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); in dpll_msg_add_pin_dplls()
607 const struct dpll_pin_properties *prop = &pin->prop; in dpll_cmd_pin_get_one()
611 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); in dpll_cmd_pin_get_one()
618 module_name(pin->module))) in dpll_cmd_pin_get_one()
619 return -EMSGSIZE; in dpll_cmd_pin_get_one()
620 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), in dpll_cmd_pin_get_one()
621 &pin->clock_id, DPLL_A_PIN_PAD)) in dpll_cmd_pin_get_one()
622 return -EMSGSIZE; in dpll_cmd_pin_get_one()
623 if (prop->board_label && in dpll_cmd_pin_get_one()
624 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) in dpll_cmd_pin_get_one()
625 return -EMSGSIZE; in dpll_cmd_pin_get_one()
626 if (prop->panel_label && in dpll_cmd_pin_get_one()
627 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) in dpll_cmd_pin_get_one()
628 return -EMSGSIZE; in dpll_cmd_pin_get_one()
629 if (prop->package_label && in dpll_cmd_pin_get_one()
631 prop->package_label)) in dpll_cmd_pin_get_one()
632 return -EMSGSIZE; in dpll_cmd_pin_get_one()
633 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) in dpll_cmd_pin_get_one()
634 return -EMSGSIZE; in dpll_cmd_pin_get_one()
635 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) in dpll_cmd_pin_get_one()
636 return -EMSGSIZE; in dpll_cmd_pin_get_one()
641 prop->phase_range.min)) in dpll_cmd_pin_get_one()
642 return -EMSGSIZE; in dpll_cmd_pin_get_one()
644 prop->phase_range.max)) in dpll_cmd_pin_get_one()
645 return -EMSGSIZE; in dpll_cmd_pin_get_one()
655 if (!xa_empty(&pin->ref_sync_pins)) in dpll_cmd_pin_get_one()
659 if (xa_empty(&pin->parent_refs)) in dpll_cmd_pin_get_one()
676 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) in dpll_device_get_one()
677 return -EMSGSIZE; in dpll_device_get_one()
678 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), in dpll_device_get_one()
679 &dpll->clock_id, DPLL_A_PAD)) in dpll_device_get_one()
680 return -EMSGSIZE; in dpll_device_get_one()
696 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) in dpll_device_get_one()
697 return -EMSGSIZE; in dpll_device_get_one()
712 int ret = -ENOMEM; in dpll_device_event_send()
715 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) in dpll_device_event_send()
716 return -ENODEV; in dpll_device_event_send()
719 return -ENOMEM; in dpll_device_event_send()
756 * dpll_device_change_ntf - notify that the dpll device has been changed
778 int ret = -ENOMEM; in dpll_pin_event_send()
782 return -ENODEV; in dpll_pin_event_send()
786 return -ENOMEM; in dpll_pin_event_send()
823 * dpll_pin_change_ntf - notify that the pin has been changed
849 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { in dpll_phase_offset_monitor_set()
851 return -EOPNOTSUPP; in dpll_phase_offset_monitor_set()
853 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, in dpll_phase_offset_monitor_set()
862 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, in dpll_phase_offset_monitor_set()
873 if (!ops->phase_offset_avg_factor_set) { in dpll_phase_offset_avg_factor_set()
876 return -EOPNOTSUPP; in dpll_phase_offset_avg_factor_set()
879 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, in dpll_phase_offset_avg_factor_set()
896 return -EINVAL; in dpll_pin_freq_set()
899 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_freq_set()
901 if (!ops->frequency_set || !ops->frequency_get) { in dpll_pin_freq_set()
903 return -EOPNOTSUPP; in dpll_pin_freq_set()
906 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); in dpll_pin_freq_set()
908 dpll = ref->dpll; in dpll_pin_freq_set()
909 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_pin_freq_set()
918 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_freq_set()
920 dpll = ref->dpll; in dpll_pin_freq_set()
921 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_freq_set()
926 dpll->id); in dpll_pin_freq_set()
935 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_freq_set()
939 dpll = ref->dpll; in dpll_pin_freq_set()
940 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_freq_set()
960 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_esync_set()
962 if (!ops->esync_set || !ops->esync_get) { in dpll_pin_esync_set()
964 "embedded sync feature is not supported by this device"); in dpll_pin_esync_set()
965 return -EOPNOTSUPP; in dpll_pin_esync_set()
968 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); in dpll_pin_esync_set()
970 dpll = ref->dpll; in dpll_pin_esync_set()
971 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_pin_esync_set()
974 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); in dpll_pin_esync_set()
984 "requested embedded sync frequency value is not supported by this device"); in dpll_pin_esync_set()
985 return -EINVAL; in dpll_pin_esync_set()
988 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_esync_set()
992 dpll = ref->dpll; in dpll_pin_esync_set()
994 ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), in dpll_pin_esync_set()
999 "embedded sync frequency set failed for dpll_id: %u", in dpll_pin_esync_set()
1000 dpll->id); in dpll_pin_esync_set()
1009 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_esync_set()
1015 dpll = ref->dpll; in dpll_pin_esync_set()
1017 if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), in dpll_pin_esync_set()
1019 NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); in dpll_pin_esync_set()
1039 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, in dpll_pin_ref_sync_state_set()
1042 NL_SET_ERR_MSG(extack, "reference sync pin not found"); in dpll_pin_ref_sync_state_set()
1043 return -EINVAL; in dpll_pin_ref_sync_state_set()
1046 NL_SET_ERR_MSG(extack, "reference sync pin not available"); in dpll_pin_ref_sync_state_set()
1047 return -EINVAL; in dpll_pin_ref_sync_state_set()
1049 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); in dpll_pin_ref_sync_state_set()
1052 if (!ops->ref_sync_set || !ops->ref_sync_get) { in dpll_pin_ref_sync_state_set()
1053 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); in dpll_pin_ref_sync_state_set()
1054 return -EOPNOTSUPP; in dpll_pin_ref_sync_state_set()
1056 dpll = ref->dpll; in dpll_pin_ref_sync_state_set()
1057 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_ref_sync_state_set()
1062 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); in dpll_pin_ref_sync_state_set()
1067 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_ref_sync_state_set()
1069 dpll = ref->dpll; in dpll_pin_ref_sync_state_set()
1070 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_ref_sync_state_set()
1077 NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", in dpll_pin_ref_sync_state_set()
1078 dpll->id); in dpll_pin_ref_sync_state_set()
1087 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_ref_sync_state_set()
1091 dpll = ref->dpll; in dpll_pin_ref_sync_state_set()
1092 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_ref_sync_state_set()
1096 NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); in dpll_pin_ref_sync_state_set()
1112 NL_SET_ERR_MSG(extack, "sync pin id expected"); in dpll_pin_ref_sync_set()
1113 return -EINVAL; in dpll_pin_ref_sync_set()
1118 NL_SET_ERR_MSG(extack, "sync pin state expected"); in dpll_pin_ref_sync_set()
1119 return -EINVAL; in dpll_pin_ref_sync_set()
1140 pin->prop.capabilities)) { in dpll_pin_on_pin_state_set()
1142 return -EOPNOTSUPP; in dpll_pin_on_pin_state_set()
1146 return -EINVAL; in dpll_pin_on_pin_state_set()
1147 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); in dpll_pin_on_pin_state_set()
1149 return -EINVAL; in dpll_pin_on_pin_state_set()
1150 xa_for_each(&parent->dpll_refs, i, dpll_ref) { in dpll_pin_on_pin_state_set()
1152 if (!ops->state_on_pin_set) in dpll_pin_on_pin_state_set()
1153 return -EOPNOTSUPP; in dpll_pin_on_pin_state_set()
1155 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); in dpll_pin_on_pin_state_set()
1156 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, in dpll_pin_on_pin_state_set()
1176 pin->prop.capabilities)) { in dpll_pin_state_set()
1178 return -EOPNOTSUPP; in dpll_pin_state_set()
1180 ref = xa_load(&pin->dpll_refs, dpll->id); in dpll_pin_state_set()
1183 if (!ops->state_on_dpll_set) in dpll_pin_state_set()
1184 return -EOPNOTSUPP; in dpll_pin_state_set()
1185 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_state_set()
1203 pin->prop.capabilities)) { in dpll_pin_prio_set()
1205 return -EOPNOTSUPP; in dpll_pin_prio_set()
1207 ref = xa_load(&pin->dpll_refs, dpll->id); in dpll_pin_prio_set()
1210 if (!ops->prio_set) in dpll_pin_prio_set()
1211 return -EOPNOTSUPP; in dpll_pin_prio_set()
1212 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, in dpll_pin_prio_set()
1231 pin->prop.capabilities)) { in dpll_pin_direction_set()
1233 return -EOPNOTSUPP; in dpll_pin_direction_set()
1235 ref = xa_load(&pin->dpll_refs, dpll->id); in dpll_pin_direction_set()
1238 if (!ops->direction_set) in dpll_pin_direction_set()
1239 return -EOPNOTSUPP; in dpll_pin_direction_set()
1240 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_direction_set()
1261 if (phase_adj > pin->prop.phase_range.max || in dpll_pin_phase_adj_set()
1262 phase_adj < pin->prop.phase_range.min) { in dpll_pin_phase_adj_set()
1265 return -EINVAL; in dpll_pin_phase_adj_set()
1268 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_phase_adj_set()
1270 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { in dpll_pin_phase_adj_set()
1272 return -EOPNOTSUPP; in dpll_pin_phase_adj_set()
1275 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); in dpll_pin_phase_adj_set()
1277 dpll = ref->dpll; in dpll_pin_phase_adj_set()
1278 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_phase_adj_set()
1288 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_phase_adj_set()
1290 dpll = ref->dpll; in dpll_pin_phase_adj_set()
1291 ret = ops->phase_adjust_set(pin, in dpll_pin_phase_adj_set()
1299 dpll->id); in dpll_pin_phase_adj_set()
1308 xa_for_each(&pin->dpll_refs, i, ref) { in dpll_pin_phase_adj_set()
1312 dpll = ref->dpll; in dpll_pin_phase_adj_set()
1313 if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), in dpll_pin_phase_adj_set()
1337 return -EINVAL; in dpll_pin_parent_device_set()
1343 return -EINVAL; in dpll_pin_parent_device_set()
1345 ref = xa_load(&pin->dpll_refs, dpll->id); in dpll_pin_parent_device_set()
1348 return -EINVAL; in dpll_pin_parent_device_set()
1383 return -EINVAL; in dpll_pin_parent_pin_set()
1404 nla_for_each_attr(a, genlmsg_data(info->genlhdr), in dpll_pin_set_from_nlattr()
1405 genlmsg_len(info->genlhdr), rem) { in dpll_pin_set_from_nlattr()
1408 ret = dpll_pin_freq_set(pin, a, info->extack); in dpll_pin_set_from_nlattr()
1413 ret = dpll_pin_phase_adj_set(pin, a, info->extack); in dpll_pin_set_from_nlattr()
1418 ret = dpll_pin_parent_device_set(pin, a, info->extack); in dpll_pin_set_from_nlattr()
1423 ret = dpll_pin_parent_pin_set(pin, a, info->extack); in dpll_pin_set_from_nlattr()
1428 ret = dpll_pin_esync_set(pin, a, info->extack); in dpll_pin_set_from_nlattr()
1433 ret = dpll_pin_ref_sync_set(pin, a, info->extack); in dpll_pin_set_from_nlattr()
1456 prop = &pin->prop; in dpll_pin_find()
1457 cid_match = clock_id ? pin->clock_id == clock_id : true; in dpll_pin_find()
1458 mod_match = mod_name_attr && module_name(pin->module) ? in dpll_pin_find()
1460 module_name(pin->module)) : true; in dpll_pin_find()
1461 type_match = type ? prop->type == type : true; in dpll_pin_find()
1462 board_match = board_label ? (prop->board_label ? in dpll_pin_find()
1463 !nla_strcmp(board_label, prop->board_label) : false) : in dpll_pin_find()
1465 panel_match = panel_label ? (prop->panel_label ? in dpll_pin_find()
1466 !nla_strcmp(panel_label, prop->panel_label) : false) : in dpll_pin_find()
1468 package_match = package_label ? (prop->package_label ? in dpll_pin_find()
1469 !nla_strcmp(package_label, prop->package_label) : in dpll_pin_find()
1475 return ERR_PTR(-EINVAL); in dpll_pin_find()
1482 return ERR_PTR(-ENODEV); in dpll_pin_find()
1495 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), in dpll_pin_find_from_nlattr()
1496 genlmsg_len(info->genlhdr), rem) { in dpll_pin_find_from_nlattr()
1534 NL_SET_ERR_MSG(info->extack, "missing attributes"); in dpll_pin_find_from_nlattr()
1535 return ERR_PTR(-EINVAL); in dpll_pin_find_from_nlattr()
1539 info->extack); in dpll_pin_find_from_nlattr()
1541 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); in dpll_pin_find_from_nlattr()
1542 return ERR_PTR(-EINVAL); in dpll_pin_find_from_nlattr()
1554 return -ENOMEM; in dpll_nl_pin_id_get_doit()
1559 return -EMSGSIZE; in dpll_nl_pin_id_get_doit()
1568 return -ENODEV; in dpll_nl_pin_id_get_doit()
1582 struct dpll_pin *pin = info->user_ptr[0]; in dpll_nl_pin_get_doit()
1588 return -ENODEV; in dpll_nl_pin_get_doit()
1591 return -ENOMEM; in dpll_nl_pin_get_doit()
1596 return -EMSGSIZE; in dpll_nl_pin_get_doit()
1598 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); in dpll_nl_pin_get_doit()
1618 ctx->idx) { in dpll_nl_pin_get_dumpit()
1621 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, in dpll_nl_pin_get_dumpit()
1622 cb->nlh->nlmsg_seq, in dpll_nl_pin_get_dumpit()
1626 ret = -EMSGSIZE; in dpll_nl_pin_get_dumpit()
1629 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); in dpll_nl_pin_get_dumpit()
1638 if (ret == -EMSGSIZE) { in dpll_nl_pin_get_dumpit()
1639 ctx->idx = i; in dpll_nl_pin_get_dumpit()
1640 return skb->len; in dpll_nl_pin_get_dumpit()
1647 struct dpll_pin *pin = info->user_ptr[0]; in dpll_nl_pin_set_doit()
1661 cid_match = clock_id ? dpll->clock_id == clock_id : true; in dpll_device_find()
1662 mod_match = mod_name_attr ? (module_name(dpll->module) ? in dpll_device_find()
1664 module_name(dpll->module)) : false) : true; in dpll_device_find()
1665 type_match = type ? dpll->type == type : true; in dpll_device_find()
1669 return ERR_PTR(-EINVAL); in dpll_device_find()
1676 return ERR_PTR(-ENODEV); in dpll_device_find()
1690 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), in dpll_device_find_from_nlattr()
1691 genlmsg_len(info->genlhdr), rem) { in dpll_device_find_from_nlattr()
1713 NL_SET_ERR_MSG(info->extack, "missing attributes"); in dpll_device_find_from_nlattr()
1714 return ERR_PTR(-EINVAL); in dpll_device_find_from_nlattr()
1716 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); in dpll_device_find_from_nlattr()
1718 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); in dpll_device_find_from_nlattr()
1719 return ERR_PTR(-EINVAL); in dpll_device_find_from_nlattr()
1731 return -ENOMEM; in dpll_nl_device_id_get_doit()
1736 return -EMSGSIZE; in dpll_nl_device_id_get_doit()
1756 struct dpll_device *dpll = info->user_ptr[0]; in dpll_nl_device_get_doit()
1763 return -ENOMEM; in dpll_nl_device_get_doit()
1768 return -EMSGSIZE; in dpll_nl_device_get_doit()
1771 ret = dpll_device_get_one(dpll, msg, info->extack); in dpll_nl_device_get_doit()
1787 nla_for_each_attr(a, genlmsg_data(info->genlhdr), in dpll_set_from_nlattr()
1788 genlmsg_len(info->genlhdr), rem) { in dpll_set_from_nlattr()
1792 info->extack); in dpll_set_from_nlattr()
1798 info->extack); in dpll_set_from_nlattr()
1810 struct dpll_device *dpll = info->user_ptr[0]; in dpll_nl_device_set_doit()
1825 ctx->idx) { in dpll_nl_device_get_dumpit()
1826 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, in dpll_nl_device_get_dumpit()
1827 cb->nlh->nlmsg_seq, &dpll_nl_family, in dpll_nl_device_get_dumpit()
1830 ret = -EMSGSIZE; in dpll_nl_device_get_dumpit()
1833 ret = dpll_device_get_one(dpll, skb, cb->extack); in dpll_nl_device_get_dumpit()
1842 if (ret == -EMSGSIZE) { in dpll_nl_device_get_dumpit()
1843 ctx->idx = i; in dpll_nl_device_get_dumpit()
1844 return skb->len; in dpll_nl_device_get_dumpit()
1855 return -EINVAL; in dpll_pre_doit()
1858 id = nla_get_u32(info->attrs[DPLL_A_ID]); in dpll_pre_doit()
1859 info->user_ptr[0] = dpll_device_get_by_id(id); in dpll_pre_doit()
1860 if (!info->user_ptr[0]) { in dpll_pre_doit()
1861 NL_SET_ERR_MSG(info->extack, "device not found"); in dpll_pre_doit()
1867 return -ENODEV; in dpll_pre_doit()
1899 ret = -EINVAL; in dpll_pin_pre_doit()
1902 info->user_ptr[0] = xa_load(&dpll_pin_xa, in dpll_pin_pre_doit()
1903 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); in dpll_pin_pre_doit()
1904 if (!info->user_ptr[0] || in dpll_pin_pre_doit()
1905 !dpll_pin_available(info->user_ptr[0])) { in dpll_pin_pre_doit()
1906 NL_SET_ERR_MSG(info->extack, "pin not found"); in dpll_pin_pre_doit()
1907 ret = -ENODEV; in dpll_pin_pre_doit()