Lines Matching +full:0 +full:x104000
6 #define QM_DFX_BASE 0x0100000
7 #define QM_DFX_STATE1 0x0104000
8 #define QM_DFX_STATE2 0x01040C8
9 #define QM_DFX_COMMON 0x0000
10 #define QM_DFX_BASE_LEN 0x5A
11 #define QM_DFX_STATE1_LEN 0x2E
12 #define QM_DFX_STATE2_LEN 0x11
13 #define QM_DFX_COMMON_LEN 0xC3
16 #define QM_XQC_ADDR_MASK GENMASK(31, 0)
17 #define CURRENT_FUN_MASK GENMASK(5, 0)
19 #define QM_SQE_ADDR_MASK GENMASK(7, 0)
21 #define QM_DFX_MB_CNT_VF 0x104010
22 #define QM_DFX_DB_CNT_VF 0x104020
23 #define QM_DFX_SQE_CNT_VF_SQN 0x104030
24 #define QM_DFX_CQE_CNT_VF_CQN 0x104040
26 #define QM_DFX_CNT_CLR_CE 0x100118
28 #define QM_IN_IDLE_ST_REG 0x1040e4
29 #define QM_IN_IDLE_STATE 0x1
63 {"QM_ECC_1BIT_CNT ", 0x104000},
64 {"QM_ECC_MBIT_CNT ", 0x104008},
65 {"QM_DFX_MB_CNT ", 0x104018},
66 {"QM_DFX_DB_CNT ", 0x104028},
67 {"QM_DFX_SQE_CNT ", 0x104038},
68 {"QM_DFX_CQE_CNT ", 0x104048},
69 {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050},
70 {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058},
71 {"QM_DFX_ACC_FINISH_CNT ", 0x104060},
72 {"QM_DFX_CQE_ERR_CNT ", 0x1040b4},
73 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200},
74 {"QM_ECC_1BIT_INF ", 0x104004},
75 {"QM_ECC_MBIT_INF ", 0x10400c},
76 {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0},
77 {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4},
78 {"QM_DFX_AXI_RDY_VLD ", 0x1040a8},
79 {"QM_DFX_FF_ST0 ", 0x1040c8},
80 {"QM_DFX_FF_ST1 ", 0x1040cc},
81 {"QM_DFX_FF_ST2 ", 0x1040d0},
82 {"QM_DFX_FF_ST3 ", 0x1040d4},
83 {"QM_DFX_FF_ST4 ", 0x1040d8},
84 {"QM_DFX_FF_ST5 ", 0x1040dc},
85 {"QM_DFX_FF_ST6 ", 0x1040e0},
86 {"QM_IN_IDLE_ST ", 0x1040e4},
87 {"QM_CACHE_CTL ", 0x100050},
88 {"QM_TIMEOUT_CFG ", 0x100070},
89 {"QM_DB_TIMEOUT_CFG ", 0x100074},
90 {"QM_FLR_PENDING_TIME_CFG ", 0x100078},
91 {"QM_ARUSR_MCFG1 ", 0x100088},
92 {"QM_AWUSR_MCFG1 ", 0x100098},
93 {"QM_AXI_M_CFG_ENABLE ", 0x1000B0},
94 {"QM_RAS_CE_THRESHOLD ", 0x1000F8},
95 {"QM_AXI_TIMEOUT_CTRL ", 0x100120},
96 {"QM_AXI_TIMEOUT_STATUS ", 0x100124},
97 {"QM_CQE_AGGR_TIMEOUT_CTRL ", 0x100144},
98 {"ACC_RAS_MSI_INT_SEL ", 0x1040fc},
99 {"QM_CQE_OUT ", 0x104100},
100 {"QM_EQE_OUT ", 0x104104},
101 {"QM_AEQE_OUT ", 0x104108},
102 {"QM_DB_INFO0 ", 0x104180},
103 {"QM_DB_INFO1 ", 0x104184},
104 {"QM_AM_CTRL_GLOBAL ", 0x300000},
105 {"QM_AM_CURR_PORT_STS ", 0x300100},
106 {"QM_AM_CURR_TRANS_RETURN ", 0x300150},
107 {"QM_AM_CURR_RD_MAX_TXID ", 0x300154},
108 {"QM_AM_CURR_WR_MAX_TXID ", 0x300158},
109 {"QM_AM_ALARM_RRESP ", 0x300180},
110 {"QM_AM_ALARM_BRESP ", 0x300184},
114 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200},
162 for (i = 0; i < info_size; i += BYTE_PER_DW, info_curr += BYTE_PER_DW) { in dump_show()
178 ret = kstrtou32(s, 0, &qp_id); in qm_sqc_dump()
180 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_sqc_dump()
190 return 0; in qm_sqc_dump()
202 return 0; in qm_sqc_dump()
215 ret = kstrtou32(s, 0, &qp_id); in qm_cqc_dump()
217 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_cqc_dump()
227 return 0; in qm_cqc_dump()
239 return 0; in qm_cqc_dump()
267 ret = qm_set_and_get_xqc(qm, cmd, xeqc, 0, 1); in qm_eqc_aeqc_dump()
294 ret = kstrtou32(presult, 0, q_id); in q_dump_param_parse()
296 dev_err(dev, "Please input qp num (0-%u)", qp_num - 1); in q_dump_param_parse()
306 ret = kstrtou32(presult, 0, e_id); in q_dump_param_parse()
308 dev_err(dev, "Please input sqe num (0-%u)", q_depth - 1); in q_dump_param_parse()
317 return 0; in q_dump_param_parse()
345 return 0; in qm_sq_dump()
363 return 0; in qm_cq_dump()
378 ret = kstrtou32(s, 0, &xeqe_id); in qm_eq_aeq_dump()
391 dev_err(dev, "Please input eqe or aeqe num (0-%u)", xeq_depth - 1); in qm_eq_aeq_dump()
432 return 0; in qm_dbg_help()
494 for (i = 0; i < table_size; i++) { in qm_cmd_write_dump()
521 return 0; in qm_cmd_write()
529 ret = 0; in qm_cmd_write()
546 *cmd_buf_tmp = '\0'; in qm_cmd_write()
592 for (i = 0; i < regs_len; i++) { in hisi_qm_regs_dump()
594 seq_printf(s, "%s= 0x%08x\n", regs[i].name, val); in hisi_qm_regs_dump()
619 return 0; in qm_regs_show()
644 return 0; in current_q_write()
652 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
660 return 0; in clear_enable_write()
712 return 0; in current_qm_write()
765 if (*pos != 0) in qm_debug_write()
766 return 0; in qm_debug_write()
773 if (len < 0) in qm_debug_write()
776 tbuf[len] = '\0'; in qm_debug_write()
777 if (kstrtoul(tbuf, 0, &val)) in qm_debug_write()
824 for (i = 0; i < reg_len; i++) { in dfx_regs_uninit()
845 for (i = 0; i < reg_len; i++) { in dfx_regs_init()
856 for (j = 0; j < diff_regs[i].reg_len; j++) { in dfx_regs_init()
866 while (i > 0) { in dfx_regs_init()
894 return 0; in qm_diff_regs_init()
915 return 0; in qm_last_regs_init()
921 for (i = 0; i < dfx_regs_num; i++) { in qm_last_regs_init()
926 return 0; in qm_last_regs_init()
952 return 0; in hisi_qm_regs_debugfs_init()
966 return 0; in hisi_qm_regs_debugfs_init()
1006 for (i = 0; i < regs_len; i++) { in hisi_qm_acc_diff_regs_dump()
1010 for (j = 0; j < dregs[i].reg_len; j++) { in hisi_qm_acc_diff_regs_dump()
1014 seq_printf(s, "0x%08x = 0x%08x ---> 0x%08x\n", in hisi_qm_acc_diff_regs_dump()
1034 for (i = 0; i < ARRAY_SIZE(qm_dfx_regs); i++) { in hisi_qm_show_last_dfx_regs()
1037 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n", in hisi_qm_show_last_dfx_regs()
1049 return 0; in qm_diff_regs_show()
1072 return 0; in qm_state_show()
1114 atomic64_set((atomic64_t *)data, 0); in qm_debugfs_atomic64_set()
1116 return 0; in qm_debugfs_atomic64_set()
1123 return 0; in qm_debugfs_atomic64_get()
1171 for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) { in hisi_qm_debug_init()
1195 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); in hisi_qm_debug_regs_clear()
1196 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); in hisi_qm_debug_regs_clear()
1199 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); in hisi_qm_debug_regs_clear()
1200 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); in hisi_qm_debug_regs_clear()
1206 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE); in hisi_qm_debug_regs_clear()
1209 for (i = 0; i < CNT_CYC_REGS_NUM; i++) { in hisi_qm_debug_regs_clear()
1215 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE); in hisi_qm_debug_regs_clear()