Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
87 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
103 .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
109 "pll-cpu", "pll-cpu" };
114 "cpu", "pll-periph" };
149 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
151 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
153 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
155 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
157 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
159 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
161 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
164 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
166 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb",
168 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb",
170 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb",
172 static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb",
174 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
176 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb",
178 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb",
181 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb",
183 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb",
185 static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb",
187 static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb",
189 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb",
191 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb",
193 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb",
195 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb",
197 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb",
199 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb",
201 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb",
203 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb",
206 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
231 static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
232 "pll-audio-4x",
233 "pll-audio-2x",
234 "pll-audio" };
251 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
254 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
256 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
258 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",
259 "pll-ddr", 0x100, BIT(2), 0);
260 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
262 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
264 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
267 static const char * const de_parents[] = { "pll-video", "pll-periph" };
269 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
273 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
277 static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
284 static const char * const deinterlace_parents[] = { "pll-video",
285 "pll-video-2x" };
291 static const char * const tve_clk2_parents[] = { "pll-video",
292 "pll-video-2x" };
294 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
297 static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
300 static const char * const tvd_parents[] = { "pll-video", "osc24M",
301 "pll-video-2x" };
305 static const char * const csi_parents[] = { "pll-video", "osc24M" };
311 * TODO: BSP says the parent is pll-audio, however common sense and experience
312 * told us it should be pll-ve. pll-ve is totally not used in BSP code.
314 static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
316 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
390 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
393 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
396 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
399 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
402 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
545 /* Force the PLL-Audio-1x divider to 4 */ in suniv_f1c100s_ccu_probe()
550 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &suniv_ccu_desc); in suniv_f1c100s_ccu_probe()
554 /* Gate then ungate PLL CPU after any rate changes */ in suniv_f1c100s_ccu_probe()
557 /* Reparent CPU during PLL CPU rate changes */ in suniv_f1c100s_ccu_probe()
565 { .compatible = "allwinner,suniv-f1c100s-ccu" },
573 .name = "suniv-f1c100s-ccu",