Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * pll audio).
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
105 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
111 2, /* post-div */
114 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
127 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
129 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
131 * This is not supported here. We hardcode the PLL to MIPI mode.
134 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
135 "pll-video", 0x040,
143 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
173 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
180 "pll-cpux" , "pll-cpux" };
187 "axi" , "pll-periph" };
223 "pll-periph" , "pll-periph" };
230 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
232 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
234 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
236 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
238 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
240 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
242 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
244 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
246 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
248 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
250 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
252 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
254 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
256 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
259 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
261 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
263 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
265 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
267 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
269 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
271 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
273 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
275 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
277 static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
280 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
282 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
284 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
286 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
289 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
291 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
293 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
295 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
297 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
299 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
301 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
303 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
306 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
371 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
372 "pll-audio-2x", "pll-audio" };
380 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
382 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
384 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
386 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
388 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
391 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
394 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
395 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
398 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
400 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
402 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
404 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
406 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
409 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
410 "pll-gpu", "pll-de" };
412 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
420 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
421 "pll-mipi" };
423 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
428 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
430 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
434 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
435 "pll-mipi", "pll-ve" };
437 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
441 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
444 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
448 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
451 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
453 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
458 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
459 "pll-ddr0", "pll-ddr1" };
463 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
465 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
469 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
471 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
479 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
482 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
589 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
592 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
595 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
598 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
601 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
604 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
798 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a33_ccu_probe()
803 /* Force PLL-MIPI to MIPI mode */ in sun8i_a33_ccu_probe()
808 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc); in sun8i_a33_ccu_probe()
812 /* Gate then ungate PLL CPU after any rate changes */ in sun8i_a33_ccu_probe()
815 /* Reparent CPU during PLL CPU rate changes */ in sun8i_a33_ccu_probe()
823 { .compatible = "allwinner,sun8i-a33-ccu" },
831 .name = "sun8i-a33-ccu",