Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-a23-a33.h"
39 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
50 * With sigma-delta modulation for fractional-N on the audio PLL,
64 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
86 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
98 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
107 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
113 2, /* post-div */
116 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
129 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
131 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
133 * This is not supported here. We hardcode the PLL to MIPI mode.
136 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
137 "pll-video", 0x040,
145 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
157 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
170 "pll-cpux" , "pll-cpux" };
177 "axi" , "pll-periph" };
213 "pll-periph" , "pll-periph" };
220 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
222 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
224 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
226 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
228 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
230 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
232 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
234 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
236 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
238 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
240 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
242 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
244 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
247 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
249 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
251 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
253 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
255 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
257 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
259 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
261 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
263 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
266 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
268 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
270 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
272 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
275 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
277 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
279 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
281 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
283 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
285 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
287 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
289 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
292 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
350 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
351 "pll-audio-2x", "pll-audio" };
359 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
361 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
363 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
365 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
367 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
370 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
372 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
374 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
376 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
378 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
381 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
382 "pll-gpu", "pll-de" };
384 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
388 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
392 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
393 "pll-mipi" };
395 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
400 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
402 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
406 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
407 "pll-mipi", "pll-ve" };
409 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
413 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
420 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
423 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
428 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
429 "pll-ddr" };
433 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
435 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
439 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
441 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
449 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
452 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
552 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
555 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
558 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
561 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
564 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
567 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
737 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a23_ccu_probe()
742 /* Force PLL-MIPI to MIPI mode */ in sun8i_a23_ccu_probe()
747 return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a23_ccu_desc); in sun8i_a23_ccu_probe()
751 { .compatible = "allwinner,sun8i-a23-ccu" },
759 .name = "sun8i-a23-ccu",