Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * pll audio).
46 * With sigma-delta modulation for fractional-N on the audio PLL,
60 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
70 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
82 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
94 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
103 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
109 2, /* post-div */
112 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
124 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
137 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
139 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
141 * This is not supported here. We hardcode the PLL to MIPI mode.
145 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
146 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
181 "pll-cpu", "pll-cpu" };
203 "axi", "pll-periph" };
241 "pll-periph", "pll-periph" };
248 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
250 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
252 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
254 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
256 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
258 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
260 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
262 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
264 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
266 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
268 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
270 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
272 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
274 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
276 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
278 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
280 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
282 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
284 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
286 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
288 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
290 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
292 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
295 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
297 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
299 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
301 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
303 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
305 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
307 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
309 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
311 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
313 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
315 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
317 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
319 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
321 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
323 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
326 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
328 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
330 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
332 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
334 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
336 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
339 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
341 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
343 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
345 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
347 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
349 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
351 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
353 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
355 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
357 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
360 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
470 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
471 "pll-audio-2x", "pll-audio" };
480 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
482 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
484 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
486 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
488 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
490 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
495 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
508 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
510 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
512 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
514 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
516 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
518 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
520 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
522 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
524 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
526 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
528 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
530 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
533 static const char * const de_parents[] = { "pll-video0", "pll-video1",
534 "pll-periph-2x", "pll-gpu",
545 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
550 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
551 "pll-video0-2x",
552 "pll-video1-2x", "pll-mipi" };
553 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
555 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
558 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
559 "pll-video0-2x",
560 "pll-video1-2x" };
561 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
564 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
568 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
569 "pll9", "pll10", "pll-mipi",
570 "pll-ve" };
571 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
574 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
583 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
596 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
603 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
606 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
610 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
619 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
621 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
622 "pll-ddr" };
637 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
640 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
643 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
647 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
649 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
651 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
653 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
656 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
657 "pll-video0", "pll-video1",
675 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
694 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
713 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
757 .hw.init = CLK_HW_INIT_PARENTS("out-a",
778 .hw.init = CLK_HW_INIT_PARENTS("out-b",
799 .hw.init = CLK_HW_INIT_PARENTS("out-c",
964 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
967 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
970 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
973 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
976 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
979 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
982 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1240 /* Force the PLL-Audio-1x divider to 1 */ in sun6i_a31_ccu_probe()
1245 /* Force PLL-MIPI to MIPI mode */ in sun6i_a31_ccu_probe()
1252 /* set PLL6 pre-div = 3 */ in sun6i_a31_ccu_probe()
1255 /* select PLL6 / pre-div */ in sun6i_a31_ccu_probe()
1260 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun6i_a31_ccu_desc); in sun6i_a31_ccu_probe()
1271 { .compatible = "allwinner,sun6i-a31-ccu" },
1279 .name = "sun6i-a31-ccu",