24  * PLL configuration register bits for PLL3200 C32
35  * PLL configuration register bits for PLL4600 C28
93 	{ .name = "clk-s-a0-pll-odf-0", },
154 	{ .name = "clockgen-a9-pll-odf", },
179 	{ .name = "clockgen-a9-pll-odf", },
188  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
198  * PLL clock that is integrated in the ClockGenA instances on the STiH415
202  * @regs_base: base of the PLL configuration register(s).
230 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_is_locked()  local
231 	u32 locked = CLKGEN_READ(pll, locked_status);  in clkgen_pll_is_locked()
238 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_is_enabled()  local
239 	u32 poweroff = CLKGEN_READ(pll, pdn_status);  in clkgen_pll_is_enabled()
245 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in __clkgen_pll_enable()  local
246 	void __iomem *base =  pll->regs_base;  in __clkgen_pll_enable()
247 	struct clkgen_field *field = &pll->data->locked_status;  in __clkgen_pll_enable()
254 	CLKGEN_WRITE(pll, pdn_ctrl, 0);  in __clkgen_pll_enable()
260 		if (pll->data->switch2pll_en)  in __clkgen_pll_enable()
261 			CLKGEN_WRITE(pll, switch2pll, 0);  in __clkgen_pll_enable()
271 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_enable()  local
275 	if (pll->lock)  in clkgen_pll_enable()
276 		spin_lock_irqsave(pll->lock, flags);  in clkgen_pll_enable()
280 	if (pll->lock)  in clkgen_pll_enable()
281 		spin_unlock_irqrestore(pll->lock, flags);  in clkgen_pll_enable()
288 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in __clkgen_pll_disable()  local
293 	if (pll->data->switch2pll_en)  in __clkgen_pll_disable()
294 		CLKGEN_WRITE(pll, switch2pll, 1);  in __clkgen_pll_disable()
296 	CLKGEN_WRITE(pll, pdn_ctrl, 1);  in __clkgen_pll_disable()
303 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in clkgen_pll_disable()  local
306 	if (pll->lock)  in clkgen_pll_disable()
307 		spin_lock_irqsave(pll->lock, flags);  in clkgen_pll_disable()
311 	if (pll->lock)  in clkgen_pll_disable()
312 		spin_unlock_irqrestore(pll->lock, flags);  in clkgen_pll_disable()
316 			  struct stm_pll *pll)  in clk_pll3200c32_get_params()  argument
349 			pll->idf  = i;  in clk_pll3200c32_get_params()
350 			pll->ndiv = n;  in clk_pll3200c32_get_params()
359 	for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)  in clk_pll3200c32_get_params()
365 static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,  in clk_pll3200c32_get_rate()  argument
368 	if (!pll->idf)  in clk_pll3200c32_get_rate()
369 		pll->idf = 1;  in clk_pll3200c32_get_rate()
371 	*rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;  in clk_pll3200c32_get_rate()
379 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in recalc_stm_pll3200c32()  local
386 	ndiv = CLKGEN_READ(pll, ndiv);  in recalc_stm_pll3200c32()
387 	idf = CLKGEN_READ(pll, idf);  in recalc_stm_pll3200c32()
422 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in set_rate_stm_pll3200c32()  local
441 	pll->ndiv = params.ndiv;  in set_rate_stm_pll3200c32()
442 	pll->idf = params.idf;  in set_rate_stm_pll3200c32()
443 	pll->cp = params.cp;  in set_rate_stm_pll3200c32()
447 	if (pll->lock)  in set_rate_stm_pll3200c32()
448 		spin_lock_irqsave(pll->lock, flags);  in set_rate_stm_pll3200c32()
450 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in set_rate_stm_pll3200c32()
451 	CLKGEN_WRITE(pll, idf, pll->idf);  in set_rate_stm_pll3200c32()
452 	CLKGEN_WRITE(pll, cp, pll->cp);  in set_rate_stm_pll3200c32()
454 	if (pll->lock)  in set_rate_stm_pll3200c32()
455 		spin_unlock_irqrestore(pll->lock, flags);  in set_rate_stm_pll3200c32()
462 /* PLL output structure
477 			  struct stm_pll *pll)  in clk_pll4600c28_get_params()  argument
508 				pll->idf  = i;  in clk_pll4600c28_get_params()
509 				pll->ndiv = n;  in clk_pll4600c28_get_params()
521 static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,  in clk_pll4600c28_get_rate()  argument
524 	if (!pll->idf)  in clk_pll4600c28_get_rate()
525 		pll->idf = 1;  in clk_pll4600c28_get_rate()
527 	*rate = (input / pll->idf) * 2 * pll->ndiv;  in clk_pll4600c28_get_rate()
535 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in recalc_stm_pll4600c28()  local
542 	params.ndiv = CLKGEN_READ(pll, ndiv);  in recalc_stm_pll4600c28()
543 	params.idf = CLKGEN_READ(pll, idf);  in recalc_stm_pll4600c28()
576 	struct clkgen_pll *pll = to_clkgen_pll(hw);  in set_rate_stm_pll4600c28()  local
600 	pll->ndiv = params.ndiv;  in set_rate_stm_pll4600c28()
601 	pll->idf = params.idf;  in set_rate_stm_pll4600c28()
605 	if (pll->lock)  in set_rate_stm_pll4600c28()
606 		spin_lock_irqsave(pll->lock, flags);  in set_rate_stm_pll4600c28()
608 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in set_rate_stm_pll4600c28()
609 	CLKGEN_WRITE(pll, idf, pll->idf);  in set_rate_stm_pll4600c28()
611 	if (pll->lock)  in set_rate_stm_pll4600c28()
612 		spin_unlock_irqrestore(pll->lock, flags);  in set_rate_stm_pll4600c28()
649 	struct clkgen_pll *pll;  in clkgen_pll_register()  local
653 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in clkgen_pll_register()
654 	if (!pll)  in clkgen_pll_register()
664 	pll->data = pll_data;  in clkgen_pll_register()
665 	pll->regs_base = reg;  in clkgen_pll_register()
666 	pll->hw.init = &init;  in clkgen_pll_register()
667 	pll->lock = lock;  in clkgen_pll_register()
669 	clk = clk_register(NULL, &pll->hw);  in clkgen_pll_register()
671 		kfree(pll);  in clkgen_pll_register()