1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
16 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
17 #include "renesas-cpg-mssr.h"
74 	/* Core Clock Outputs exported to DT */
80 	/* Internal Core Clocks */
127 	/* Internal Core Clocks */
157 	/* Core output clk */
203 static struct clk * __init
205 			       const struct cpg_core_clk *core,  in r9a09g077_cpg_div_clk_register()  argument
208 	const struct clk *parent;  in r9a09g077_cpg_div_clk_register()
212 	parent = pub->clks[core->parent];  in r9a09g077_cpg_div_clk_register()
218 	if (core->dtable)  in r9a09g077_cpg_div_clk_register()
219 		clk_hw = clk_hw_register_divider_table(dev, core->name,  in r9a09g077_cpg_div_clk_register()
222 						       GET_SHIFT(core->conf),  in r9a09g077_cpg_div_clk_register()
223 						       GET_WIDTH(core->conf),  in r9a09g077_cpg_div_clk_register()
224 						       core->flag,  in r9a09g077_cpg_div_clk_register()
225 						       core->dtable,  in r9a09g077_cpg_div_clk_register()
226 						       &pub->rmw_lock);  in r9a09g077_cpg_div_clk_register()
228 		clk_hw = clk_hw_register_divider(dev, core->name,  in r9a09g077_cpg_div_clk_register()
231 						 GET_SHIFT(core->conf),  in r9a09g077_cpg_div_clk_register()
232 						 GET_WIDTH(core->conf),  in r9a09g077_cpg_div_clk_register()
233 						 core->flag, &pub->rmw_lock);  in r9a09g077_cpg_div_clk_register()
238 	return clk_hw->clk;  in r9a09g077_cpg_div_clk_register()
242 static struct clk * __init
244 			       const struct cpg_core_clk *core,  in r9a09g077_cpg_mux_clk_register()  argument
249 	clk_hw = devm_clk_hw_register_mux(dev, core->name,  in r9a09g077_cpg_mux_clk_register()
250 					  core->parent_names, core->num_parents,  in r9a09g077_cpg_mux_clk_register()
251 					  core->flag,  in r9a09g077_cpg_mux_clk_register()
253 					  GET_SHIFT(core->conf),  in r9a09g077_cpg_mux_clk_register()
254 					  GET_WIDTH(core->conf),  in r9a09g077_cpg_mux_clk_register()
255 					  core->mux_flags, &pub->rmw_lock);  in r9a09g077_cpg_mux_clk_register()
259 	return clk_hw->clk;  in r9a09g077_cpg_mux_clk_register()
262 static struct clk * __init
263 r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core,  in r9a09g077_cpg_clk_register()  argument
267 	u32 offset = GET_REG_OFFSET(core->conf);  in r9a09g077_cpg_clk_register()
268 	void __iomem *base = RZT2H_REG_BLOCK(offset) ? pub->base1 : pub->base0;  in r9a09g077_cpg_clk_register()
271 	switch (core->type) {  in r9a09g077_cpg_clk_register()
273 		return r9a09g077_cpg_div_clk_register(dev, core, addr, pub);  in r9a09g077_cpg_clk_register()
275 		return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub);  in r9a09g077_cpg_clk_register()
277 		return ERR_PTR(-EINVAL);  in r9a09g077_cpg_clk_register()
282 	/* Core Clocks */