Lines Matching +full:10 +full:- +full:11
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
105 {1, 10},
203 BUS_MSTOP(10, BIT(11))),
205 BUS_MSTOP(10, BIT(12))),
211 BUS_MSTOP(5, BIT(10))),
213 BUS_MSTOP(5, BIT(11))),
219 BUS_MSTOP(11, BIT(13))),
221 BUS_MSTOP(11, BIT(14))),
223 BUS_MSTOP(11, BIT(15))),
224 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
226 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
227 BUS_MSTOP(3, BIT(10))),
229 BUS_MSTOP(3, BIT(10))),
243 BUS_MSTOP(11, BIT(0))),
245 BUS_MSTOP(11, BIT(0))),
247 BUS_MSTOP(11, BIT(0))),
249 BUS_MSTOP(11, BIT(1))),
251 BUS_MSTOP(11, BIT(1))),
253 BUS_MSTOP(11, BIT(1))),
254 DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
255 BUS_MSTOP(11, BIT(2))),
256 DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
257 BUS_MSTOP(11, BIT(2))),
259 BUS_MSTOP(11, BIT(2))),
263 BUS_MSTOP(10, BIT(15))),
265 BUS_MSTOP(10, BIT(15))),
267 BUS_MSTOP(10, BIT(15))),
282 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
284 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
288 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
290 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
292 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
294 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
296 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
298 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
300 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
302 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
304 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
306 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
308 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
310 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
312 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
314 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
316 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
318 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
320 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
322 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
323 BUS_MSTOP(7, BIT(10))),
324 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
325 BUS_MSTOP(7, BIT(11))),
326 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
328 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
330 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
332 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
334 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
336 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
338 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
340 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
366 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
368 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
391 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
404 DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
414 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
415 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
416 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
421 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
422 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
423 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
424 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
425 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
426 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
427 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
428 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
429 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
430 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
431 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
432 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
438 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
439 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */