Lines Matching +full:3 +full:- +full:4
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
75 {2, 4},
76 {3, 8},
82 {1, 4},
88 {1, 4},
90 {3, 16},
96 {1, 4},
98 {3, 16},
99 {4, 64},
125 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
126 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
127 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
129 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
133 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
134 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
154 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
157 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
169 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
200 BUS_MSTOP(3, BIT(2))),
202 BUS_MSTOP(3, BIT(3))),
203 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
205 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
209 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
210 BUS_MSTOP(3, BIT(5))),
211 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17,
213 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18,
215 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
217 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
219 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
228 BUS_MSTOP(11, BIT(3))),
230 BUS_MSTOP(11, BIT(3))),
232 BUS_MSTOP(11, BIT(3))),
233 DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
234 BUS_MSTOP(11, BIT(3))),
235 DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
236 BUS_MSTOP(11, BIT(3))),
237 DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
238 BUS_MSTOP(11, BIT(4))),
239 DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
240 BUS_MSTOP(11, BIT(4))),
241 DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
242 BUS_MSTOP(11, BIT(4))),
243 DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
244 BUS_MSTOP(11, BIT(4))),
245 DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
246 BUS_MSTOP(11, BIT(4))),
247 DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
249 DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
251 DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
253 DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
255 DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
257 DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
259 DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
261 DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
263 DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
265 DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
267 DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
269 DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
271 DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
273 DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
275 DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
277 DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
279 DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
281 DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
283 DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
285 DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
287 DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
289 DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
291 DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
293 DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
295 DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
297 DEF_MOD("rsci7_pclk", CLK_PLLCLN_DIV16, 8, 0, 4, 0,
299 DEF_MOD("rsci7_tclk", CLK_PLLCLN_DIV16, 8, 1, 4, 1,
301 DEF_MOD("rsci7_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
303 DEF_MOD("rsci7_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 3, 4, 3,
305 DEF_MOD("rsci7_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 4, 4, 4,
307 DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
309 DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
311 DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
313 DEF_MOD("rsci8_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 8, 4, 8,
315 DEF_MOD("rsci8_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 9, 4, 9,
317 DEF_MOD("rsci9_pclk", CLK_PLLCLN_DIV16, 8, 10, 4, 10,
319 DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
321 DEF_MOD("rsci9_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
323 DEF_MOD("rsci9_ps_ps2_n", CLK_PLLCLN_DIV256, 8, 13, 4, 13,
325 DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
327 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
328 BUS_MSTOP(3, BIT(14))),
329 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
331 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
333 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
335 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
336 BUS_MSTOP(3, BIT(13))),
337 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
339 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
341 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
342 BUS_MSTOP(1, BIT(3))),
343 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
344 BUS_MSTOP(1, BIT(4))),
345 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
347 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
349 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
351 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
353 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
355 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
357 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
359 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
360 BUS_MSTOP(4, BIT(5))),
362 BUS_MSTOP(4, BIT(5))),
364 BUS_MSTOP(4, BIT(5))),
365 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
367 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
374 BUS_MSTOP(8, BIT(3))),
376 BUS_MSTOP(8, BIT(3))),
378 BUS_MSTOP(8, BIT(3))),
380 BUS_MSTOP(8, BIT(3))),
382 BUS_MSTOP(8, BIT(4))),
384 BUS_MSTOP(8, BIT(4))),
386 BUS_MSTOP(8, BIT(4))),
388 BUS_MSTOP(8, BIT(4))),
393 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
395 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
425 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
428 BUS_MSTOP(9, BIT(4))),
429 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
430 BUS_MSTOP(9, BIT(4))),
431 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
432 BUS_MSTOP(9, BIT(4))),
434 BUS_MSTOP(3, BIT(4))),
436 BUS_MSTOP(3, BIT(4))),
438 BUS_MSTOP(3, BIT(4))),
444 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
445 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
446 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
447 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
448 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
449 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
450 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
451 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
452 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
457 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
458 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
459 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
460 DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
461 DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
462 DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
463 DEF_RST(8, 4, 3, 21), /* RSCI1_TRESETN */
464 DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
465 DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
466 DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
467 DEF_RST(8, 8, 3, 25), /* RSCI3_TRESETN */
468 DEF_RST(8, 9, 3, 26), /* RSCI4_PRESETN */
469 DEF_RST(8, 10, 3, 27), /* RSCI4_TRESETN */
470 DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
471 DEF_RST(8, 12, 3, 29), /* RSCI5_TRESETN */
472 DEF_RST(8, 13, 3, 30), /* RSCI6_PRESETN */
473 DEF_RST(8, 14, 3, 31), /* RSCI6_TRESETN */
474 DEF_RST(8, 15, 4, 0), /* RSCI7_PRESETN */
475 DEF_RST(9, 0, 4, 1), /* RSCI7_TRESETN */
476 DEF_RST(9, 1, 4, 2), /* RSCI8_PRESETN */
477 DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
478 DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
479 DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
480 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
481 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
482 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
483 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
484 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
485 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
486 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
487 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
488 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
489 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
490 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
491 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
492 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
493 DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
494 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
495 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
496 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
497 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
498 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
499 DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
500 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
501 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
502 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */