1 // SPDX-License-Identifier: GPL-2.0
3  * sh73a0 Core CPG Clocks
8 #include <linux/clk-provider.h>
72 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,  in sh73a0_cpg_register_clock()  argument
89 		u32 enable_bit = name[3] - '0';  in sh73a0_cpg_register_clock()
106 			return ERR_PTR(-EINVAL);  in sh73a0_cpg_register_clock()
116 		u32 phy_no = name[3] - '0';  in sh73a0_cpg_register_clock()
135 		for (c = div4_clks; c->name; c++) {  in sh73a0_cpg_register_clock()
136 			if (!strcmp(name, c->name)) {  in sh73a0_cpg_register_clock()
137 				parent_name = c->parent;  in sh73a0_cpg_register_clock()
139 				reg = c->reg;  in sh73a0_cpg_register_clock()
140 				shift = c->shift;  in sh73a0_cpg_register_clock()
145 		if (!c->name)  in sh73a0_cpg_register_clock()
146 			return ERR_PTR(-EINVAL);  in sh73a0_cpg_register_clock()
155 						  table, &cpg->lock);  in sh73a0_cpg_register_clock()
161 	struct sh73a0_cpg *cpg;  in sh73a0_cpg_clocks_init()  local
167 	num_clks = of_property_count_strings(np, "clock-output-names");  in sh73a0_cpg_clocks_init()
173 	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);  in sh73a0_cpg_clocks_init()
175 	if (cpg == NULL || clks == NULL) {  in sh73a0_cpg_clocks_init()
182 	spin_lock_init(&cpg->lock);  in sh73a0_cpg_clocks_init()
184 	cpg->data.clks = clks;  in sh73a0_cpg_clocks_init()
185 	cpg->data.clk_num = num_clks;  in sh73a0_cpg_clocks_init()
200 		of_property_read_string_index(np, "clock-output-names", i,  in sh73a0_cpg_clocks_init()
203 		clk = sh73a0_cpg_register_clock(np, cpg, base, name);  in sh73a0_cpg_clocks_init()
208 			cpg->data.clks[i] = clk;  in sh73a0_cpg_clocks_init()
211 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in sh73a0_cpg_clocks_init()
213 CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",