Lines Matching +full:0 +full:x1004
23 #define CX_GMU_CBCR_SLEEP_MASK 0xf
25 #define CX_GMU_CBCR_WAKE_MASK 0xf
37 { 249600000, 2000000000, 0 },
41 .l = 0x1a,
42 .alpha = 0xaaa,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00002261,
45 .config_ctl_hi1_val = 0x029a699c,
46 .user_ctl_val = 0x00000000,
47 .user_ctl_hi_val = 0x00000805,
48 .user_ctl_hi1_val = 0x00000000,
52 .offset = 0x100,
69 { P_BI_TCXO, 0 },
83 F(19200000, P_BI_TCXO, 1, 0, 0),
84 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
85 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
90 .cmd_rcgr = 0x1120,
91 .mnd_width = 0,
105 .halt_reg = 0x1078,
108 .enable_reg = 0x1078,
109 .enable_mask = BIT(0),
118 .halt_reg = 0x107c,
121 .enable_reg = 0x107c,
122 .enable_mask = BIT(0),
131 .halt_reg = 0x1088,
134 .enable_reg = 0x1088,
135 .enable_mask = BIT(0),
144 .halt_reg = 0x1098,
147 .enable_reg = 0x1098,
148 .enable_mask = BIT(0),
162 .halt_reg = 0x108c,
165 .enable_reg = 0x108c,
166 .enable_mask = BIT(0),
175 .halt_reg = 0x1004,
178 .enable_reg = 0x1004,
179 .enable_mask = BIT(0),
188 .halt_reg = 0x109c,
191 .enable_reg = 0x109c,
192 .enable_mask = BIT(0),
201 .halt_reg = 0x1064,
204 .enable_reg = 0x1064,
205 .enable_mask = BIT(0),
219 .halt_reg = 0x5000,
222 .enable_reg = 0x5000,
223 .enable_mask = BIT(0),
232 .gdscr = 0x106c,
233 .gds_hw_ctrl = 0x1540,
242 .gdscr = 0x100c,
243 .clamp_io_ctrl = 0x1508,
267 [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
268 [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
269 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
270 [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
271 [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
272 [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
284 .max_register = 0x8008,
321 value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; in gpu_cc_sm8250_probe()
322 regmap_update_bits(regmap, 0x1098, mask, value); in gpu_cc_sm8250_probe()