Lines Matching +full:0 +full:xa010
44 { 249600000, 2000000000, 0 },
49 .l = 0x3e,
50 .alpha = 0x8000,
51 .post_div_mask = 0xff << 8,
52 .post_div_val = 0x31 << 8,
53 .test_ctl_val = 0x40000000,
57 .offset = 0x0,
101 .l = 0x23,
102 .alpha = 0x6aaa,
103 .post_div_mask = 0xf << 8,
104 .post_div_val = 0x1 << 8,
105 .test_ctl_val = 0x40000000,
109 .offset = 0x1000,
141 .l = 0x64,
142 .config_ctl_hi_val = 0x400003d6,
143 .config_ctl_val = 0x20000954,
144 .user_ctl_val = 0x0000030b,
148 .offset = 0x2000,
176 .offset = 0x2000,
192 .offset = 0x2000,
209 .l = 0x27,
210 .alpha = 0x9555,
211 .post_div_mask = 0xf << 8,
212 .post_div_val = 0x1 << 8,
213 .test_ctl_val = 0x40000000,
217 .offset = 0x3000,
248 .offset = 0x4000,
279 { P_BI_TCXO, 0 },
295 { P_BI_TCXO, 0 },
313 { P_BI_TCXO_MX, 0 },
323 { P_BI_TCXO, 0 },
341 { P_BI_TCXO, 0 },
351 { P_BI_TCXO, 0 },
361 { P_BI_TCXO, 0 },
371 { P_CHIP_SLEEP_CLK, 0 },
379 { P_BI_TCXO, 0 },
389 { P_BI_TCXO, 0 },
397 F(19200000, P_BI_TCXO, 1, 0, 0),
398 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
399 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
400 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
401 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
402 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
407 .cmd_rcgr = 0x7010,
408 .mnd_width = 0,
421 F(19200000, P_BI_TCXO, 1, 0, 0),
422 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
423 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
424 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
425 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
426 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
431 .cmd_rcgr = 0xc12c,
432 .mnd_width = 0,
445 F(19200000, P_BI_TCXO, 1, 0, 0),
446 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
451 .cmd_rcgr = 0xc0c4,
465 .cmd_rcgr = 0xc0e0,
479 F(19200000, P_BI_TCXO, 1, 0, 0),
480 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
481 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
482 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
487 .cmd_rcgr = 0xa064,
488 .mnd_width = 0,
501 F(19200000, P_BI_TCXO, 1, 0, 0),
502 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
507 .cmd_rcgr = 0x6004,
508 .mnd_width = 0,
521 .cmd_rcgr = 0x6028,
522 .mnd_width = 0,
535 .cmd_rcgr = 0x604c,
536 .mnd_width = 0,
549 .cmd_rcgr = 0x6070,
550 .mnd_width = 0,
563 F(19200000, P_BI_TCXO, 1, 0, 0),
564 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0),
565 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
566 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
567 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
568 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
573 .cmd_rcgr = 0x703c,
574 .mnd_width = 0,
587 F(19200000, P_BI_TCXO, 1, 0, 0),
588 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
589 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
590 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
591 F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0),
592 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
597 .cmd_rcgr = 0xc09c,
598 .mnd_width = 0,
612 F(19200000, P_BI_TCXO, 1, 0, 0),
613 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
614 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
619 .cmd_rcgr = 0xc074,
620 .mnd_width = 0,
633 F(19200000, P_BI_TCXO, 1, 0, 0),
634 F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
635 F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
636 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
637 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
642 .cmd_rcgr = 0xa010,
643 .mnd_width = 0,
657 F(19200000, P_BI_TCXO, 1, 0, 0),
658 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
659 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
660 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
661 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
666 .cmd_rcgr = 0xa03c,
667 .mnd_width = 0,
680 F(19200000, P_BI_TCXO, 1, 0, 0),
681 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
682 F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
683 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
684 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
689 .cmd_rcgr = 0xb010,
690 .mnd_width = 0,
704 .cmd_rcgr = 0xb034,
705 .mnd_width = 0,
718 F(19200000, P_BI_TCXO, 1, 0, 0),
719 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
720 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
721 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
722 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
727 .cmd_rcgr = 0xc004,
728 .mnd_width = 0,
741 .cmd_rcgr = 0xc020,
742 .mnd_width = 0,
755 F(19200000, P_BI_TCXO, 1, 0, 0),
756 F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
757 F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
758 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
759 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
764 .cmd_rcgr = 0x8010,
765 .mnd_width = 0,
779 .cmd_rcgr = 0xc048,
780 .mnd_width = 0,
793 F(19200000, P_BI_TCXO, 1, 0, 0),
794 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
795 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
796 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
797 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
798 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
803 .cmd_rcgr = 0xc100,
804 .mnd_width = 0,
817 F(19200000, P_BI_TCXO_MX, 1, 0, 0),
819 F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0),
824 .cmd_rcgr = 0x5004,
838 .cmd_rcgr = 0x5024,
852 .cmd_rcgr = 0x5044,
866 .cmd_rcgr = 0x5064,
880 F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
885 .cmd_rcgr = 0xc1a4,
886 .mnd_width = 0,
899 F(19200000, P_BI_TCXO, 1, 0, 0),
900 F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0),
905 .cmd_rcgr = 0x7058,
906 .mnd_width = 0,
919 F(19200000, P_BI_TCXO, 1, 0, 0),
924 .cmd_rcgr = 0xc188,
925 .mnd_width = 0,
938 .halt_reg = 0x7070,
941 .enable_reg = 0x7070,
942 .enable_mask = BIT(0),
956 .halt_reg = 0x7054,
959 .enable_reg = 0x7054,
960 .enable_mask = BIT(0),
974 .halt_reg = 0x7038,
977 .enable_reg = 0x7038,
978 .enable_mask = BIT(0),
992 .halt_reg = 0x7028,
995 .enable_reg = 0x7028,
996 .enable_mask = BIT(0),
1010 .halt_reg = 0xc148,
1013 .enable_reg = 0xc148,
1014 .enable_mask = BIT(0),
1028 .halt_reg = 0xc150,
1031 .enable_reg = 0xc150,
1032 .enable_mask = BIT(0),
1046 .halt_reg = 0xc0dc,
1049 .enable_reg = 0xc0dc,
1050 .enable_mask = BIT(0),
1064 .halt_reg = 0xc0f8,
1067 .enable_reg = 0xc0f8,
1068 .enable_mask = BIT(0),
1082 .halt_reg = 0xc184,
1085 .enable_reg = 0xc184,
1086 .enable_mask = BIT(0),
1100 .halt_reg = 0xc124,
1103 .enable_reg = 0xc124,
1104 .enable_mask = BIT(0),
1118 .halt_reg = 0x601c,
1121 .enable_reg = 0x601c,
1122 .enable_mask = BIT(0),
1136 .halt_reg = 0x6040,
1139 .enable_reg = 0x6040,
1140 .enable_mask = BIT(0),
1154 .halt_reg = 0x6064,
1157 .enable_reg = 0x6064,
1158 .enable_mask = BIT(0),
1172 .halt_reg = 0x6088,
1175 .enable_reg = 0x6088,
1176 .enable_mask = BIT(0),
1190 .halt_reg = 0x6020,
1193 .enable_reg = 0x6020,
1194 .enable_mask = BIT(0),
1208 .halt_reg = 0x6044,
1211 .enable_reg = 0x6044,
1212 .enable_mask = BIT(0),
1226 .halt_reg = 0x6068,
1229 .enable_reg = 0x6068,
1230 .enable_mask = BIT(0),
1244 .halt_reg = 0x608c,
1247 .enable_reg = 0x608c,
1248 .enable_mask = BIT(0),
1262 .halt_reg = 0xc0b4,
1265 .enable_reg = 0xc0b4,
1266 .enable_mask = BIT(0),
1280 .halt_reg = 0xc0bc,
1283 .enable_reg = 0xc0bc,
1284 .enable_mask = BIT(0),
1298 .halt_reg = 0xc094,
1301 .enable_reg = 0xc094,
1302 .enable_mask = BIT(0),
1316 .halt_reg = 0xc08c,
1319 .enable_reg = 0xc08c,
1320 .enable_mask = BIT(0),
1334 .halt_reg = 0xa080,
1337 .enable_reg = 0xa080,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0xa028,
1355 .enable_reg = 0xa028,
1356 .enable_mask = BIT(0),
1370 .halt_reg = 0xa07c,
1373 .enable_reg = 0xa07c,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0xa054,
1391 .enable_reg = 0xa054,
1392 .enable_mask = BIT(0),
1406 .halt_reg = 0xa038,
1409 .enable_reg = 0xa038,
1410 .enable_mask = BIT(0),
1424 .halt_reg = 0xb058,
1427 .enable_reg = 0xb058,
1428 .enable_mask = BIT(0),
1442 .halt_reg = 0xb028,
1445 .enable_reg = 0xb028,
1446 .enable_mask = BIT(0),
1460 .halt_reg = 0xb054,
1463 .enable_reg = 0xb054,
1464 .enable_mask = BIT(0),
1478 .halt_reg = 0xb04c,
1481 .enable_reg = 0xb04c,
1482 .enable_mask = BIT(0),
1496 .halt_reg = 0xb030,
1499 .enable_reg = 0xb030,
1500 .enable_mask = BIT(0),
1514 .halt_reg = 0xc01c,
1517 .enable_reg = 0xc01c,
1518 .enable_mask = BIT(0),
1532 .halt_reg = 0xc040,
1535 .enable_reg = 0xc040,
1536 .enable_mask = BIT(0),
1550 .halt_reg = 0xc038,
1553 .enable_reg = 0xc038,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0x8040,
1571 .enable_reg = 0x8040,
1572 .enable_mask = BIT(0),
1586 .halt_reg = 0x803c,
1589 .enable_reg = 0x803c,
1590 .enable_mask = BIT(0),
1604 .halt_reg = 0x8038,
1607 .enable_reg = 0x8038,
1608 .enable_mask = BIT(0),
1622 .halt_reg = 0x8028,
1625 .enable_reg = 0x8028,
1626 .enable_mask = BIT(0),
1640 .halt_reg = 0x9028,
1643 .enable_reg = 0x9028,
1644 .enable_mask = BIT(0),
1658 .halt_reg = 0x9024,
1661 .enable_reg = 0x9024,
1662 .enable_mask = BIT(0),
1676 .halt_reg = 0x9020,
1679 .enable_reg = 0x9020,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x9010,
1697 .enable_reg = 0x9010,
1698 .enable_mask = BIT(0),
1712 .halt_reg = 0xc060,
1715 .enable_reg = 0xc060,
1716 .enable_mask = BIT(0),
1730 .halt_reg = 0xc118,
1733 .enable_reg = 0xc118,
1734 .enable_mask = BIT(0),
1748 .halt_reg = 0x501c,
1751 .enable_reg = 0x501c,
1752 .enable_mask = BIT(0),
1766 .halt_reg = 0x503c,
1769 .enable_reg = 0x503c,
1770 .enable_mask = BIT(0),
1784 .halt_reg = 0x505c,
1787 .enable_reg = 0x505c,
1788 .enable_mask = BIT(0),
1802 .halt_reg = 0x507c,
1805 .enable_reg = 0x507c,
1806 .enable_mask = BIT(0),
1820 .halt_reg = 0xc1bc,
1823 .enable_reg = 0xc1bc,
1824 .enable_mask = BIT(0),
1840 .gdscr = 0x7004,
1850 .gdscr = 0xa004,
1860 .gdscr = 0xb004,
1870 .gdscr = 0x8004,
1880 .gdscr = 0x9004,
1890 .gdscr = 0xc1c4,
2008 .max_register = 0xd024,
2043 qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */ in camcc_sm7150_probe()