Lines Matching +full:sar2130p +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
242 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 	  the output clocks to the networking hardware and GCC blocks.
702 	tristate "SAR2130P Global Clock Controller"
706 	  Support for the global clock controller on SAR2130P devices.
711 	tristate "SAR2130P Graphics clock controller"
715 	  Support for the graphics clock controller on SAR2130P devices.
1154 	  SAR2130P, SM8550 or SM8650 devices.
1411 	  Say Y if you want to toggle LPASS-adjacent resets within
1529 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1531 	  Support for the high-frequency PLLs present on Qualcomm devices.
1538 	  Support for the Krait ACC and GCC clock controllers. Say Y