65 /* Fractional PLL operating modes */
78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)  in pll_readl()  argument
80 	return readl(pll->base + reg);  in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)  in pll_writel()  argument
85 	writel(val, pll->base + reg);  in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll)  in pll_lock()  argument
90 	while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))  in pll_lock()
107 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_frac_get_mode()  local
110 	val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;  in pll_frac_get_mode()
116 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_frac_set_mode()  local
119 	val = pll_readl(pll, PLL_CTRL3);  in pll_frac_set_mode()
125 	pll_writel(pll, val, PLL_CTRL3);  in pll_frac_set_mode()
129 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,  in pll_get_params()  argument
134 	for (i = 0; i < pll->nr_rates; i++) {  in pll_get_params()
135 		if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)  in pll_get_params()
136 			return &pll->rates[i];  in pll_get_params()
145 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_round_rate()  local
148 	for (i = 0; i < pll->nr_rates; i++) {  in pll_round_rate()
149 		if (i > 0 && pll->rates[i].fref == *parent_rate &&  in pll_round_rate()
150 		    pll->rates[i].fout <= rate)  in pll_round_rate()
151 			return pll->rates[i - 1].fout;  in pll_round_rate()
154 	return pll->rates[0].fout;  in pll_round_rate()
159 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_enable()  local
162 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_enable()
165 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_enable()
167 	val = pll_readl(pll, PLL_CTRL4);  in pll_gf40lp_frac_enable()
169 	pll_writel(pll, val, PLL_CTRL4);  in pll_gf40lp_frac_enable()
171 	pll_lock(pll);  in pll_gf40lp_frac_enable()
178 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_disable()  local
181 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_disable()
183 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_disable()
188 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_is_enabled()  local
190 	return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);  in pll_gf40lp_frac_is_enabled()
196 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_set_rate()  local
205 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_frac_set_rate()
226 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
231 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
233 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
242 		pr_warn("%s: changing postdiv while PLL is enabled\n", name);  in pll_gf40lp_frac_set_rate()
255 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
264 		pll_lock(pll);  in pll_gf40lp_frac_set_rate()
272 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_recalc_rate()  local
275 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_recalc_rate()
279 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_recalc_rate()
316 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_enable()  local
319 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_enable()
322 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_enable()
324 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_laint_enable()
326 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_laint_enable()
328 	pll_lock(pll);  in pll_gf40lp_laint_enable()
335 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_disable()  local
338 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_disable()
340 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_disable()
345 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_is_enabled()  local
347 	return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);  in pll_gf40lp_laint_is_enabled()
353 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_set_rate()  local
362 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_laint_set_rate()
379 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
388 		pr_warn("%s: changing postdiv while PLL is enabled\n", name);  in pll_gf40lp_laint_set_rate()
401 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
404 		pll_lock(pll);  in pll_gf40lp_laint_set_rate()
412 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_recalc_rate()  local
416 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_recalc_rate()
452 	struct pistachio_clk_pll *pll;  in pll_register()  local
456 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in pll_register()
457 	if (!pll)  in pll_register()
479 		pr_err("Unrecognized PLL type %u\n", type);  in pll_register()
480 		kfree(pll);  in pll_register()
484 	pll->hw.init = &init;  in pll_register()
485 	pll->base = base;  in pll_register()
486 	pll->rates = rates;  in pll_register()
487 	pll->nr_rates = nr_rates;  in pll_register()
489 	clk = clk_register(NULL, &pll->hw);  in pll_register()
491 		kfree(pll);  in pll_register()
497 				struct pistachio_pll *pll,  in pistachio_clk_register_pll()  argument
504 		clk = pll_register(pll[i].name, pll[i].parent,  in pistachio_clk_register_pll()
505 				   0, p->base + pll[i].reg_base,  in pistachio_clk_register_pll()
506 				   pll[i].type, pll[i].rates,  in pistachio_clk_register_pll()
507 				   pll[i].nr_rates);  in pistachio_clk_register_pll()
508 		p->clk_data.clks[pll[i].id] = clk;  in pistachio_clk_register_pll()