Lines Matching full:pclk
451 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_enable() local
455 if (pclk->lock) in xgene_clk_enable()
456 spin_lock_irqsave(pclk->lock, flags); in xgene_clk_enable()
458 if (pclk->param.csr_reg) { in xgene_clk_enable()
461 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_enable()
462 pclk->param.reg_clk_offset); in xgene_clk_enable()
463 data |= pclk->param.reg_clk_mask; in xgene_clk_enable()
464 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_enable()
465 pclk->param.reg_clk_offset); in xgene_clk_enable()
468 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, in xgene_clk_enable()
472 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_enable()
473 pclk->param.reg_csr_offset); in xgene_clk_enable()
474 data &= ~pclk->param.reg_csr_mask; in xgene_clk_enable()
475 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_enable()
476 pclk->param.reg_csr_offset); in xgene_clk_enable()
479 pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, in xgene_clk_enable()
483 if (pclk->lock) in xgene_clk_enable()
484 spin_unlock_irqrestore(pclk->lock, flags); in xgene_clk_enable()
491 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_disable() local
495 if (pclk->lock) in xgene_clk_disable()
496 spin_lock_irqsave(pclk->lock, flags); in xgene_clk_disable()
498 if (pclk->param.csr_reg) { in xgene_clk_disable()
501 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_disable()
502 pclk->param.reg_csr_offset); in xgene_clk_disable()
503 data |= pclk->param.reg_csr_mask; in xgene_clk_disable()
504 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_disable()
505 pclk->param.reg_csr_offset); in xgene_clk_disable()
508 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_disable()
509 pclk->param.reg_clk_offset); in xgene_clk_disable()
510 data &= ~pclk->param.reg_clk_mask; in xgene_clk_disable()
511 xgene_clk_write(data, pclk->param.csr_reg + in xgene_clk_disable()
512 pclk->param.reg_clk_offset); in xgene_clk_disable()
515 if (pclk->lock) in xgene_clk_disable()
516 spin_unlock_irqrestore(pclk->lock, flags); in xgene_clk_disable()
521 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_is_enabled() local
524 if (pclk->param.csr_reg) { in xgene_clk_is_enabled()
526 data = xgene_clk_read(pclk->param.csr_reg + in xgene_clk_is_enabled()
527 pclk->param.reg_clk_offset); in xgene_clk_is_enabled()
529 str_enabled_disabled(data & pclk->param.reg_clk_mask)); in xgene_clk_is_enabled()
534 return data & pclk->param.reg_clk_mask ? 1 : 0; in xgene_clk_is_enabled()
540 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_recalc_rate() local
543 if (pclk->param.divider_reg) { in xgene_clk_recalc_rate()
544 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_recalc_rate()
545 pclk->param.reg_divider_offset); in xgene_clk_recalc_rate()
546 data >>= pclk->param.reg_divider_shift; in xgene_clk_recalc_rate()
547 data &= (1 << pclk->param.reg_divider_width) - 1; in xgene_clk_recalc_rate()
564 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_set_rate() local
570 if (pclk->lock) in xgene_clk_set_rate()
571 spin_lock_irqsave(pclk->lock, flags); in xgene_clk_set_rate()
573 if (pclk->param.divider_reg) { in xgene_clk_set_rate()
578 divider &= (1 << pclk->param.reg_divider_width) - 1; in xgene_clk_set_rate()
579 divider <<= pclk->param.reg_divider_shift; in xgene_clk_set_rate()
582 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_set_rate()
583 pclk->param.reg_divider_offset); in xgene_clk_set_rate()
584 data &= ~(((1 << pclk->param.reg_divider_width) - 1) in xgene_clk_set_rate()
585 << pclk->param.reg_divider_shift); in xgene_clk_set_rate()
587 xgene_clk_write(data, pclk->param.divider_reg + in xgene_clk_set_rate()
588 pclk->param.reg_divider_offset); in xgene_clk_set_rate()
595 if (pclk->lock) in xgene_clk_set_rate()
596 spin_unlock_irqrestore(pclk->lock, flags); in xgene_clk_set_rate()
604 struct xgene_clk *pclk = to_xgene_clk(hw); in xgene_clk_determine_rate() local
608 if (pclk->param.divider_reg) { in xgene_clk_determine_rate()