315 #define VT8500_BITS_TO_FREQ(r, m, d)					\  argument
316 				((r / d) * m)
318 #define VT8500_BITS_TO_VAL(m, d)					\  argument
319 				((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
325 #define WM8650_BITS_TO_FREQ(r, m, d1, d2)				\  argument
326 				(r * m / (d1 * (1 << d2)))
328 #define WM8650_BITS_TO_VAL(m, d1, d2)					\  argument
329 				((d2 << 13) | (d1 << 10) | (m & 0x3FF))
335 #define WM8750_BITS_TO_FREQ(r, m, d1, d2)				\  argument
336 				(r * (m+1) / ((d1+1) * (1 << d2)))
338 #define WM8750_BITS_TO_VAL(f, m, d1, d2)				\  argument
339 		((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
345 #define WM8850_BITS_TO_FREQ(r, m, d1, d2)				\  argument
346 				(r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
348 #define WM8850_BITS_TO_VAL(m, d1, d2)					\  argument
349 		((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
380  * M * parent [O1] => / P [O2] => / D [O3]
382  * O2 is 600MHz >= (M * parent) / P >= 300MHz;
383  * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
386  * D = 4: 75MHz...150MHz
387  * D = 2: 150MHz...300MHz
402 	 * Divisor P cannot be calculated. Test all divisors and find where M  in wm8650_find_pll_bits()