1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
8 #include <linux/reset-controller.h>
9 #include <dt-bindings/clock/en7523-clk.h>
10 #include <dt-bindings/reset/airoha,en7581-reset.h>
260 	if (!desc->base_bits)  in en7523_get_base_rate()
261 		return desc->base_value;  in en7523_get_base_rate()
263 	val = readl(base + desc->base_reg);  in en7523_get_base_rate()
264 	val >>= desc->base_shift;  in en7523_get_base_rate()
265 	val &= (1 << desc->base_bits) - 1;  in en7523_get_base_rate()
267 	if (val >= desc->n_base_values)  in en7523_get_base_rate()
270 	return desc->base_values[val];  in en7523_get_base_rate()
278 	if (!desc->div_bits)  in en7523_get_div()
281 	reg = desc->div_reg ? desc->div_reg : desc->base_reg;  in en7523_get_div()
283 	val >>= desc->div_shift;  in en7523_get_div()
284 	val &= (1 << desc->div_bits) - 1;  in en7523_get_div()
286 	if (!val && desc->div_val0)  in en7523_get_div()
287 		return desc->div_val0;  in en7523_get_div()
289 	return (val + desc->div_offset) * desc->div_step;  in en7523_get_div()
296 	return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);  in en7523_pci_is_enabled()
302 	void __iomem *np_base = cg->base;  in en7523_pci_prepare()
341 	void __iomem *np_base = cg->base;  in en7523_pci_unprepare()
355 		.ops = &soc_data->pcie_ops,  in en7523_register_pcie_clk()
363 	cg->base = np_base;  in en7523_register_pcie_clk()
364 	cg->hw.init = &init;  in en7523_register_pcie_clk()
366 	if (init.ops->unprepare)  in en7523_register_pcie_clk()
367 		init.ops->unprepare(&cg->hw);  in en7523_register_pcie_clk()
369 	if (clk_hw_register(dev, &cg->hw))  in en7523_register_pcie_clk()
372 	return &cg->hw;  in en7523_register_pcie_clk()
381 	val = readl(cg->base + REG_PCI_CONTROL);  in en7581_pci_is_enabled()
388 	void __iomem *np_base = cg->base;  in en7581_pci_enable()
404 	void __iomem *np_base = cg->base;  in en7581_pci_disable()
454 		hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);  in en7523_register_clocks()
457 			       desc->name, PTR_ERR(hw));  in en7523_register_clocks()
461 		clk_data->hws[desc->id] = hw;  in en7523_register_clocks()
465 	clk_data->hws[EN7523_CLK_PCIE] = hw;  in en7523_register_clocks()
467 	clk_data->num = EN7523_NUM_CLOCKS;  in en7523_register_clocks()
474 	void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];  in en7523_reset_update()
503 	void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];  in en7523_reset_status()
513 	if (reset_spec->args[0] >= rcdev->nr_resets)  in en7523_reset_xlate()
514 		return -EINVAL;  in en7523_reset_xlate()
516 	return rst_data->idx_map[reset_spec->args[0]];  in en7523_reset_xlate()
528 	struct device *dev = &pdev->dev;  in en7523_reset_register()
533 	if (!soc_data->reset.idx_map_nr)  in en7523_reset_register()
542 		return -ENOMEM;  in en7523_reset_register()
544 	rst_data->bank_ofs = soc_data->reset.bank_ofs;  in en7523_reset_register()
545 	rst_data->idx_map = soc_data->reset.idx_map;  in en7523_reset_register()
546 	rst_data->base = base;  in en7523_reset_register()
548 	rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;  in en7523_reset_register()
549 	rst_data->rcdev.of_xlate = en7523_reset_xlate;  in en7523_reset_register()
550 	rst_data->rcdev.ops = &en7523_reset_ops;  in en7523_reset_register()
551 	rst_data->rcdev.of_node = dev->of_node;  in en7523_reset_register()
552 	rst_data->rcdev.of_reset_n_cells = 1;  in en7523_reset_register()
553 	rst_data->rcdev.owner = THIS_MODULE;  in en7523_reset_register()
554 	rst_data->rcdev.dev = dev;  in en7523_reset_register()
556 	return devm_reset_controller_register(dev, &rst_data->rcdev);  in en7523_reset_register()
561 	struct device_node *node = pdev->dev.of_node;  in en7523_clk_probe()
575 	soc_data = device_get_match_data(&pdev->dev);  in en7523_clk_probe()
576 	if (soc_data->hw_init) {  in en7523_clk_probe()
577 		r = soc_data->hw_init(pdev, np_base);  in en7523_clk_probe()
582 	clk_data = devm_kzalloc(&pdev->dev,  in en7523_clk_probe()
586 		return -ENOMEM;  in en7523_clk_probe()
588 	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);  in en7523_clk_probe()
592 		return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",  in en7523_clk_probe()
593 				     pdev->name);  in en7523_clk_probe()
598 		return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",  in en7523_clk_probe()
599 				     pdev->name);  in en7523_clk_probe()
628 	{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
629 	{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
636 		.name = "clk-en7523",