Lines Matching defs:map
24 static int regcache_hw_init(struct regmap *map)
32 if (!map->num_reg_defaults_raw)
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
37 if (regmap_readable(map, i * map->reg_stride) &&
38 !regmap_volatile(map, i * map->reg_stride))
43 map->cache_bypass = true;
47 map->num_reg_defaults = count;
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
50 if (!map->reg_defaults)
53 if (!map->reg_defaults_raw) {
54 bool cache_bypass = map->cache_bypass;
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
58 map->cache_bypass = true;
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
64 ret = regmap_raw_read(map, 0, tmp_buf,
65 map->cache_size_raw);
66 map->cache_bypass = cache_bypass;
68 map->reg_defaults_raw = tmp_buf;
69 map->cache_free = true;
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 reg = i * map->reg_stride;
79 if (!regmap_readable(map, reg))
82 if (regmap_volatile(map, reg))
85 if (map->reg_defaults_raw) {
86 val = regcache_get_val(map, map->reg_defaults_raw, i);
88 bool cache_bypass = map->cache_bypass;
90 map->cache_bypass = true;
91 ret = regmap_read(map, reg, &val);
92 map->cache_bypass = cache_bypass;
94 dev_err(map->dev, "Failed to read %d: %d\n",
100 map->reg_defaults[j].reg = reg;
101 map->reg_defaults[j].def = val;
108 kfree(map->reg_defaults);
113 int regcache_init(struct regmap *map, const struct regmap_config *config)
119 if (map->cache_type == REGCACHE_NONE) {
121 dev_warn(map->dev,
124 map->cache_bypass = true;
129 dev_err(map->dev,
135 dev_err(map->dev,
141 if (config->reg_defaults[i].reg % map->reg_stride)
145 if (cache_types[i]->type == map->cache_type)
149 dev_err(map->dev, "Could not match cache type: %d\n",
150 map->cache_type);
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
160 map->cache = NULL;
161 map->cache_ops = cache_types[i];
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
173 tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,
174 sizeof(*map->reg_defaults), GFP_KERNEL);
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
183 ret = regcache_hw_init(map);
186 if (map->cache_bypass)
190 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
192 map->max_register_is_set = true;
195 if (map->cache_ops->init) {
196 dev_dbg(map->dev, "Initializing %s cache\n",
197 map->cache_ops->name);
198 map->lock(map->lock_arg);
199 ret = map->cache_ops->init(map);
200 map->unlock(map->lock_arg);
207 kfree(map->reg_defaults);
208 if (map->cache_free)
209 kfree(map->reg_defaults_raw);
214 void regcache_exit(struct regmap *map)
216 if (map->cache_type == REGCACHE_NONE)
219 BUG_ON(!map->cache_ops);
221 kfree(map->reg_defaults);
222 if (map->cache_free)
223 kfree(map->reg_defaults_raw);
225 if (map->cache_ops->exit) {
226 dev_dbg(map->dev, "Destroying %s cache\n",
227 map->cache_ops->name);
228 map->lock(map->lock_arg);
229 map->cache_ops->exit(map);
230 map->unlock(map->lock_arg);
237 * @map: map to configure.
243 int regcache_read(struct regmap *map,
248 if (map->cache_type == REGCACHE_NONE)
251 BUG_ON(!map->cache_ops);
253 if (!regmap_volatile(map, reg)) {
254 ret = map->cache_ops->read(map, reg, value);
257 trace_regmap_reg_read_cache(map, reg, *value);
268 * @map: map to configure.
274 int regcache_write(struct regmap *map,
277 if (map->cache_type == REGCACHE_NONE)
280 BUG_ON(!map->cache_ops);
282 if (!regmap_volatile(map, reg))
283 return map->cache_ops->write(map, reg, value);
288 bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
293 if (!regmap_writeable(map, reg))
297 if (!map->no_sync_defaults)
301 ret = regcache_lookup_reg(map, reg);
302 if (ret >= 0 && val == map->reg_defaults[ret].def)
307 static int regcache_default_sync(struct regmap *map, unsigned int min,
312 for (reg = min; reg <= max; reg += map->reg_stride) {
316 if (regmap_volatile(map, reg) ||
317 !regmap_writeable(map, reg))
320 ret = regcache_read(map, reg, &val);
326 if (!regcache_reg_needs_sync(map, reg, val))
329 map->cache_bypass = true;
330 ret = _regmap_write(map, reg, val);
331 map->cache_bypass = false;
333 dev_err(map->dev, "Unable to sync register %#x. %d\n",
337 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
351 * @map: map to configure.
359 int regcache_sync(struct regmap *map)
367 if (WARN_ON(map->cache_type == REGCACHE_NONE))
370 BUG_ON(!map->cache_ops);
372 map->lock(map->lock_arg);
374 bypass = map->cache_bypass;
375 dev_dbg(map->dev, "Syncing %s cache\n",
376 map->cache_ops->name);
377 name = map->cache_ops->name;
378 trace_regcache_sync(map, name, "start");
380 if (!map->cache_dirty)
384 map->cache_bypass = true;
385 for (i = 0; i < map->patch_regs; i++) {
386 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
388 dev_err(map->dev, "Failed to write %x = %x: %d\n",
389 map->patch[i].reg, map->patch[i].def, ret);
393 map->cache_bypass = false;
395 if (map->cache_ops->sync)
396 ret = map->cache_ops->sync(map, 0, map->max_register);
398 ret = regcache_default_sync(map, 0, map->max_register);
401 map->cache_dirty = false;
405 map->cache_bypass = bypass;
406 map->no_sync_defaults = false;
414 rb_for_each(node, NULL, &map->range_tree, rbtree_all) {
419 if (regcache_read(map, this->selector_reg, &i) != 0)
422 ret = _regmap_write(map, this->selector_reg, i);
424 dev_err(map->dev, "Failed to write %x = %x: %d\n",
430 map->unlock(map->lock_arg);
432 regmap_async_complete(map);
434 trace_regcache_sync(map, name, "stop");
443 * @map: map to sync.
452 int regcache_sync_region(struct regmap *map, unsigned int min,
459 if (WARN_ON(map->cache_type == REGCACHE_NONE))
462 BUG_ON(!map->cache_ops);
464 map->lock(map->lock_arg);
467 bypass = map->cache_bypass;
469 name = map->cache_ops->name;
470 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
472 trace_regcache_sync(map, name, "start region");
474 if (!map->cache_dirty)
477 map->async = true;
479 if (map->cache_ops->sync)
480 ret = map->cache_ops->sync(map, min, max);
482 ret = regcache_default_sync(map, min, max);
486 map->cache_bypass = bypass;
487 map->async = false;
488 map->no_sync_defaults = false;
489 map->unlock(map->lock_arg);
491 regmap_async_complete(map);
493 trace_regcache_sync(map, name, "stop region");
502 * @map: map to operate on
510 int regcache_drop_region(struct regmap *map, unsigned int min,
515 if (!map->cache_ops || !map->cache_ops->drop)
518 map->lock(map->lock_arg);
520 trace_regcache_drop_region(map, min, max);
522 ret = map->cache_ops->drop(map, min, max);
524 map->unlock(map->lock_arg);
531 * regcache_cache_only - Put a register map into cache only mode
533 * @map: map to configure
536 * When a register map is marked as cache only writes to the register
537 * map API will only update the register cache, they will not cause
542 void regcache_cache_only(struct regmap *map, bool enable)
544 map->lock(map->lock_arg);
545 WARN_ON(map->cache_type != REGCACHE_NONE &&
546 map->cache_bypass && enable);
547 map->cache_only = enable;
548 trace_regmap_cache_only(map, enable);
549 map->unlock(map->lock_arg);
556 * @map: map to mark
566 void regcache_mark_dirty(struct regmap *map)
568 map->lock(map->lock_arg);
569 map->cache_dirty = true;
570 map->no_sync_defaults = true;
571 map->unlock(map->lock_arg);
576 * regcache_cache_bypass - Put a register map into cache bypass mode
578 * @map: map to configure
581 * When a register map is marked with the cache bypass option, writes
582 * to the register map API will only update the hardware and not
586 void regcache_cache_bypass(struct regmap *map, bool enable)
588 map->lock(map->lock_arg);
589 WARN_ON(map->cache_only && enable);
590 map->cache_bypass = enable;
591 trace_regmap_cache_bypass(map, enable);
592 map->unlock(map->lock_arg);
599 * @map: map to check
604 bool regcache_reg_cached(struct regmap *map, unsigned int reg)
609 map->lock(map->lock_arg);
611 ret = regcache_read(map, reg, &val);
613 map->unlock(map->lock_arg);
619 void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
623 if (map->format.format_val) {
624 map->format.format_val(base + (map->cache_word_size * idx),
629 switch (map->cache_word_size) {
653 unsigned int regcache_get_val(struct regmap *map, const void *base,
660 if (map->format.parse_val)
661 return map->format.parse_val(regcache_get_val_addr(map, base,
664 switch (map->cache_word_size) {
695 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
703 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
707 return r - map->reg_defaults;
720 int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
724 if (!regcache_reg_needs_sync(map, reg, val))
727 map->cache_bypass = true;
729 ret = _regmap_write(map, reg, val);
731 map->cache_bypass = false;
734 dev_err(map->dev, "Unable to sync register %#x. %d\n",
738 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
744 static int regcache_sync_block_single(struct regmap *map, void *block,
753 regtmp = block_base + (i * map->reg_stride);
756 !regmap_writeable(map, regtmp))
759 val = regcache_get_val(map, block, i);
760 ret = regcache_sync_val(map, regtmp, val);
768 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
771 size_t val_bytes = map->format.val_bytes;
777 count = (cur - base) / map->reg_stride;
779 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
780 count * val_bytes, count, base, cur - map->reg_stride);
782 map->cache_bypass = true;
784 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
786 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
787 base, cur - map->reg_stride, ret);
789 map->cache_bypass = false;
796 static int regcache_sync_block_raw(struct regmap *map, void *block,
808 regtmp = block_base + (i * map->reg_stride);
811 !regmap_writeable(map, regtmp)) {
812 ret = regcache_sync_block_raw_flush(map, &data,
819 val = regcache_get_val(map, block, i);
820 if (!regcache_reg_needs_sync(map, regtmp, val)) {
821 ret = regcache_sync_block_raw_flush(map, &data,
829 data = regcache_get_val_addr(map, block, i);
834 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
835 map->reg_stride);
838 int regcache_sync_block(struct regmap *map, void *block,
843 if (regmap_can_raw_write(map) && !map->use_single_write)
844 return regcache_sync_block_raw(map, block, cache_present,
847 return regcache_sync_block_single(map, block, cache_present,