19 #define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)  argument
46 #define MCI_STATUS_CEC(c)	(((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)  argument
129 #define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))  argument
130 #define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))  argument
131 #define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))  argument
132 #define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))  argument
133 #define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))  argument
134 #define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))  argument
135 #define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))  argument
136 #define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))  argument
137 #define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))  argument
138 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))  argument
139 #define MSR_AMD64_SMCA_MCx_SYND1(x)	(MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x))  argument
140 #define MSR_AMD64_SMCA_MCx_SYND2(x)	(MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x))  argument
142 #define XEC(x, mask)			(((x) >> 16) & mask)  argument
251 static inline void mca_bsp_init(struct cpuinfo_x86 *c) {}  in mca_bsp_init()
252 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}  in mcheck_cpu_init()
253 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}  in mcheck_cpu_clear()
273 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }  in mce_intel_feature_init()
274 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }  in mce_intel_feature_clear()
379 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }  in mce_amd_feature_init()