Lines Matching +full:sw +full:- +full:exception

1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <asm/alternative-macros.h>
17 #include <asm/asm-offsets.h>
61 	 * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6
62 	 * 	   = cpu - ((cpu >> 6) << 3) << 3
139 	 * The RISC-V kernel does not eagerly emit a sfence.vma after each
141 	 * - if the uarch caches invalid entries, the new mapping would not be
143 	 * - if the uarch does not cache invalid entries, a reordered access
153 	addi sp, sp, -(PT_SIZE_ON_STACK)
163 	addi sp, sp, -(PT_SIZE_ON_STACK)
170 	 * Disable user-mode memory access as it should only be set in the
197 	 * Set the scratch register to 0, so that if a recursive exception
198 	 * occurs, the exception vector knows it came from the kernel
229 	/* Check if exception code lies within bounds */
244  *  - handle_exception
245  *  - ret_from_fork
285 	 * reservation, so instead here we clear any existing reservation --
292 	 * forward branch around an SC -- which is how we implement CAS.  As a
332 	addi sp, sp, -(PT_SIZE_ON_STACK)
379  * Calls func(regs) using the per-CPU IRQ stack.
383 	addi	sp, sp, -STACKFRAME_SIZE_ON_STACK
388 	/* Switch to the per-CPU shadow call stack */
392 	/* Switch to the per-CPU IRQ stack and call the handler */
402 	addi	sp, s0, -STACKFRAME_SIZE_ON_STACK
413  * The callee-saved registers must be saved and restored.
422 	/* Save context into prev->thread */
447 	/* Restore context from next->thread */
479 	/* Exception vector table */
500 	RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */