Lines Matching +full:io +full:- +full:channel +full:- +full:mux
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "sophgo,cv1800b-top-syscon",
30 "syscon", "simple-mfd";
32 #address-cells = <1>;
33 #size-cells = <1>;
36 compatible = "sophgo,cv1800b-usb2-phy";
38 #phy-cells = <0>;
42 clock-names = "app", "stb", "lpm";
46 dmamux: dma-router@154 {
47 compatible = "sophgo,cv1800b-dmamux";
49 #dma-cells = <2>;
50 dma-masters = <&dmac>;
54 rst: reset-controller@3003000 {
55 compatible = "sophgo,cv1800b-reset";
57 #reset-cells = <1>;
60 mdio: mdio-mux@3009800 {
61 compatible = "mdio-mux-mmioreg", "mdio-mux";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 mdio-parent-bus = <&gmac0_mdio>;
66 mux-mask = <0x80>;
70 #address-cells = <1>;
71 #size-cells = <0>;
75 compatible = "ethernet-phy-ieee802.3-c22";
81 #address-cells = <1>;
82 #size-cells = <0>;
88 compatible = "snps,dw-apb-gpio";
90 #address-cells = <1>;
91 #size-cells = <0>;
94 porta: gpio-controller@0 {
95 compatible = "snps,dw-apb-gpio-port";
96 gpio-controller;
97 #gpio-cells = <2>;
100 interrupt-controller;
101 #interrupt-cells = <2>;
107 compatible = "snps,dw-apb-gpio";
109 #address-cells = <1>;
110 #size-cells = <0>;
113 portb: gpio-controller@0 {
114 compatible = "snps,dw-apb-gpio-port";
115 gpio-controller;
116 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
126 compatible = "snps,dw-apb-gpio";
128 #address-cells = <1>;
129 #size-cells = <0>;
132 portc: gpio-controller@0 {
133 compatible = "snps,dw-apb-gpio-port";
134 gpio-controller;
135 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
145 compatible = "snps,dw-apb-gpio";
147 #address-cells = <1>;
148 #size-cells = <0>;
151 portd: gpio-controller@0 {
152 compatible = "snps,dw-apb-gpio-port";
153 gpio-controller;
154 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
164 compatible = "sophgo,cv1800b-saradc";
168 #address-cells = <1>;
169 #size-cells = <0>;
172 channel@0 {
176 channel@1 {
180 channel@2 {
186 compatible = "snps,designware-i2c";
188 #address-cells = <1>;
189 #size-cells = <0>;
191 clock-names = "ref", "pclk";
198 compatible = "snps,designware-i2c";
200 #address-cells = <1>;
201 #size-cells = <0>;
203 clock-names = "ref", "pclk";
210 compatible = "snps,designware-i2c";
212 #address-cells = <1>;
213 #size-cells = <0>;
215 clock-names = "ref", "pclk";
222 compatible = "snps,designware-i2c";
224 #address-cells = <1>;
225 #size-cells = <0>;
227 clock-names = "ref", "pclk";
234 compatible = "snps,designware-i2c";
236 #address-cells = <1>;
237 #size-cells = <0>;
239 clock-names = "ref", "pclk";
246 compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
249 clock-names = "stmmaceth", "ptp_ref";
251 interrupt-names = "macirq";
252 phy-handle = <&internal_ephy>;
253 phy-mode = "internal";
255 reset-names = "stmmaceth";
256 rx-fifo-depth = <8192>;
257 tx-fifo-depth = <8192>;
258 snps,multicast-filter-bins = <0>;
259 snps,perfect-filter-entries = <1>;
263 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
264 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
265 snps,axi-config = <&gmac0_stmmac_axi_setup>;
269 compatible = "snps,dwmac-mdio";
270 #address-cells = <1>;
271 #size-cells = <0>;
274 gmac0_mtl_rx_setup: rx-queues-config {
275 snps,rx-queues-to-use = <1>;
279 gmac0_mtl_tx_setup: tx-queues-config {
280 snps,tx-queues-to-use = <1>;
284 gmac0_stmmac_axi_setup: stmmac-axi-config {
292 compatible = "snps,dw-apb-uart";
296 clock-names = "baudclk", "apb_pclk";
297 reg-shift = <2>;
298 reg-io-width = <4>;
304 compatible = "snps,dw-apb-uart";
308 clock-names = "baudclk", "apb_pclk";
309 reg-shift = <2>;
310 reg-io-width = <4>;
316 compatible = "snps,dw-apb-uart";
320 clock-names = "baudclk", "apb_pclk";
321 reg-shift = <2>;
322 reg-io-width = <4>;
328 compatible = "snps,dw-apb-uart";
332 clock-names = "baudclk", "apb_pclk";
333 reg-shift = <2>;
334 reg-io-width = <4>;
340 compatible = "snps,dw-apb-ssi";
342 #address-cells = <1>;
343 #size-cells = <0>;
345 clock-names = "ssi_clk", "pclk";
352 compatible = "snps,dw-apb-ssi";
354 #address-cells = <1>;
355 #size-cells = <0>;
357 clock-names = "ssi_clk", "pclk";
364 compatible = "snps,dw-apb-ssi";
366 #address-cells = <1>;
367 #size-cells = <0>;
369 clock-names = "ssi_clk", "pclk";
376 compatible = "snps,dw-apb-ssi";
378 #address-cells = <1>;
379 #size-cells = <0>;
381 clock-names = "ssi_clk", "pclk";
388 compatible = "snps,dw-apb-uart";
392 clock-names = "baudclk", "apb_pclk";
393 reg-shift = <2>;
394 reg-io-width = <4>;
400 compatible = "sophgo,cv1800b-dwcmshc";
405 clock-names = "core", "bus";
410 compatible = "sophgo,cv1800b-dwcmshc";
415 clock-names = "core", "bus";
419 dmac: dma-controller@4330000 {
420 compatible = "snps,axi-dma-1.01a";
424 clock-names = "core-clk", "cfgr-clk";
425 #dma-cells = <1>;
426 dma-channels = <8>;
427 snps,block-size = <1024 1024 1024 1024
430 snps,dma-masters = <2>;
431 snps,data-width = <2>;
436 compatible = "sophgo,cv1800b-usb";
439 clock-names = "otg", "utmi";
440 g-np-tx-fifo-size = <32>;
441 g-rx-fifo-size = <536>;
442 g-tx-fifo-size = <768 512 512 384 128 128>;
445 phy-names = "usb2-phy";
447 reset-names = "dwc2";
452 compatible = "sophgo,cv1800b-rtc", "syscon";
457 interrupt-names = "alarm", "longpress", "vbat";
460 clock-names = "rtc", "mcu";