Lines Matching full:339
5196 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5197 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5198 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5199 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5200 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5201 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5202 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5203 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5204 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5205 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5206 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5207 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5208 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5209 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5210 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5211 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5212 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5213 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5214 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5215 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5216 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5217 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5218 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5219 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5220 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5221 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5222 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5223 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5224 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5225 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5226 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5227 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5228 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5229 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5230 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5231 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5232 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5233 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5234 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5235 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5236 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5237 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5238 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5239 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5240 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5241 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5242 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5243 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5244 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5245 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5246 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5247 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5248 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5249 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5250 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5251 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5252 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5253 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5254 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5255 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5256 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5257 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5258 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5259 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5260 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5261 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5262 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5263 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5264 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5265 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5266 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5267 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5268 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5269 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5270 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5271 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5272 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5273 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5274 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5275 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5276 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5277 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5278 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5279 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5280 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5281 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5282 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5283 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5284 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5285 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5286 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5287 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5288 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5289 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5290 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5291 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5292 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5293 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5294 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5295 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5296 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5297 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5298 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5299 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5300 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5301 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5302 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5303 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5304 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5305 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5306 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5307 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5308 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5309 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5310 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5311 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5312 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5313 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5314 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5315 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5316 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5317 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5318 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5319 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5320 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5321 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5322 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5323 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5324 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5325 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5326 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5327 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5328 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5329 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5330 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5331 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5332 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5333 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5334 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5335 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5336 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5337 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5338 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5339 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5340 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5341 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5342 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5343 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5344 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5345 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5346 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5347 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5348 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5349 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5350 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5351 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5352 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5353 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5354 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5355 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5356 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5357 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5358 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5359 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5360 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5361 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5362 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5363 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5364 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5365 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5366 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5367 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5368 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5369 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5370 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5371 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5372 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5373 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5374 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5375 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5376 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5377 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5378 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5379 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5380 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5381 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5382 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5383 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5384 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5385 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5386 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5387 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5388 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5389 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5390 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5391 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5392 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5393 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5394 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5395 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5396 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},