Lines Matching +full:pcie +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
22 #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23 #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
26 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
40 __be32 potar; /* 0x.0 - Outbound translation address register */
41 __be32 potear; /* 0x.4 - Outbound translation extended address register */
42 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 u8 res1[4];
44 __be32 powar; /* 0x.10 - Outbound window attributes register */
50 __be32 pitar; /* 0x.0 - Inbound translation address register */
51 u8 res1[4];
52 __be32 piwbar; /* 0x.8 - Inbound window base address register */
53 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
54 __be32 piwar; /* 0x.10 - Inbound window attributes register */
60 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
61 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
62 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
63 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
64 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
65 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
66 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
67 u8 res2[4];
68 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
69 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
70 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
71 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
73 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
74 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
76 /* PCI/PCI Express outbound window 0-4
83 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
85 /* PCI/PCI Express inbound window 3-0
86 * inbound window 1 supports only a 32-bit base address and does not
89 struct pci_inbound_window_regs piw[4];
91 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
92 u8 res21[4];
93 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
94 u8 res22[4];
95 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
97 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
98 u8 res24[4];
99 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
100 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
101 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
102 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
104 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
106 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
110 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/