Lines Matching +full:0 +full:x10000000
74 size = <0 0x1000000>;
75 alignment = <0 0x1000000>;
78 size = <0 0x400000>;
79 alignment = <0 0x400000>;
82 size = <0 0x2000000>;
83 alignment = <0 0x2000000>;
88 reg = <0xf 0xfe124000 0 0x2000>;
89 ranges = <0 0 0xf 0xe8000000 0x08000000
90 2 0 0xf 0xff800000 0x00010000
91 3 0 0xf 0xffdf0000 0x00008000>;
93 nor@0,0 {
97 reg = <0x0 0x0 0x8000000>;
103 nand@2,0 {
107 reg = <0x2 0x0 0x10000>;
110 board-control@3,0 {
114 reg = <3 0 0x300>;
115 ranges = <0 3 0 0x300>;
119 #size-cells = <0>;
122 reg = <0x54 1>;
123 mux-mask = <0xe0>;
125 t1040mdio0: mdio@0 {
127 #size-cells = <0>;
128 reg = <0x00>;
132 reg = <0x1>;
138 #size-cells = <0>;
139 reg = <0x20>;
143 reg = <0x2>;
149 #size-cells = <0>;
150 reg = <0x60>;
154 reg = <0x1c>;
158 reg = <0x1d>;
162 reg = <0x1e>;
166 reg = <0x1f>;
172 #size-cells = <0>;
173 reg = <0xa0>;
176 reg = <0x14>;
180 reg = <0x15>;
184 reg = <0x16>;
188 reg = <0x17>;
194 #size-cells = <0>;
195 reg = <0xc0>;
198 reg = <0x18>;
202 reg = <0x19>;
206 reg = <0x1a>;
210 reg = <0x1b>;
216 #size-cells = <0>;
217 reg = <0xe0>;
221 reg = <0x1c>;
225 reg = <0x1d>;
229 reg = <0x1e>;
233 reg = <0x1f>;
245 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
249 ranges = <0x0 0xf 0xf4000000 0x2000000>;
253 ranges = <0x0 0xf 0xf6000000 0x2000000>;
257 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
258 reg = <0xf 0xfe000000 0 0x00001000>;
261 flash@0 {
265 reg = <0>;
273 reg = <0x77>;
277 reg = <0x68>;
278 interrupts = <0x1 0x1 0 0>;
284 fixed-link = <0 1 1000 0 0>;
289 fixed-link = <1 1 1000 0 0>;
311 reg = <0xf 0xfe240000 0 0x10000>;
312 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
313 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
314 pcie@0 {
315 ranges = <0x02000000 0 0xe0000000
316 0x02000000 0 0xe0000000
317 0 0x10000000
319 0x01000000 0 0x00000000
320 0x01000000 0 0x00000000
321 0 0x00010000>;
326 reg = <0xf 0xfe250000 0 0x10000>;
327 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
328 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
329 pcie@0 {
330 ranges = <0x02000000 0 0xe0000000
331 0x02000000 0 0xe0000000
332 0 0x10000000
334 0x01000000 0 0x00000000
335 0x01000000 0 0x00000000
336 0 0x00010000>;
341 reg = <0xf 0xfe260000 0 0x10000>;
342 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
343 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
344 pcie@0 {
345 ranges = <0x02000000 0 0xe0000000
346 0x02000000 0 0xe0000000
347 0 0x10000000
349 0x01000000 0 0x00000000
350 0x01000000 0 0x00000000
351 0 0x00010000>;
356 reg = <0xf 0xfe270000 0 0x10000>;
357 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
358 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
359 pcie@0 {
360 ranges = <0x02000000 0 0xe0000000
361 0x02000000 0 0xe0000000
362 0 0x10000000
364 0x01000000 0 0x00000000
365 0x01000000 0 0x00000000
366 0 0x00010000>;
371 ranges = <0x0 0xf 0xfe140000 0x40000>;
372 reg = <0xf 0xfe140000 0 0x480>;
373 brg-frequency = <0>;
374 bus-frequency = <0>;
378 reg = <0x700 0x80>;
383 reg = <0x1000 0x800>;
392 fsl,tx-timeslot-mask = <0xfffffffe>;
393 fsl,rx-timeslot-mask = <0xfffffffe>;
395 fsl,tdm-id = <0>;
396 fsl,siram-entry-id = <0>;
402 port-number = <0>;