Lines Matching +full:pcie +full:- +full:x1
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
52 pcie@0 {
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
59 interrupt-map-mask = <0xf800 0 0 7>;
61 interrupt-map = <
63 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
64 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
65 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
66 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
73 compatible = "fsl,mpc8548-pcie";
75 #size-cells = <2>;
76 #address-cells = <3>;
77 bus-range = <0 255>;
78 clock-frequency = <33333333>;
81 pcie@0 {
83 #interrupt-cells = <1>;
84 #size-cells = <2>;
85 #address-cells = <3>;
88 interrupt-map-mask = <0xf800 0 0 7>;
90 interrupt-map = <
92 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
93 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
94 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
95 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
102 compatible = "fsl,mpc8548-pcie";
104 #size-cells = <2>;
105 #address-cells = <3>;
106 bus-range = <0 255>;
107 clock-frequency = <33333333>;
110 pcie@0 {
112 #interrupt-cells = <1>;
113 #size-cells = <2>;
114 #address-cells = <3>;
117 interrupt-map-mask = <0xf800 0 0 7>;
118 interrupt-map = <
120 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
129 #address-cells = <1>;
130 #size-cells = <1>;
132 compatible = "fsl,mpc8572-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
138 fsl,num-laws = <12>;
142 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
147 memory-controller@2000 {
148 compatible = "fsl,mpc8572-memory-controller";
153 memory-controller@6000 {
154 compatible = "fsl,mpc8572-memory-controller";
159 /include/ "pq3-i2c-0.dtsi"
160 /include/ "pq3-i2c-1.dtsi"
161 /include/ "pq3-duart-0.dtsi"
162 /include/ "pq3-dma-1.dtsi"
163 /include/ "pq3-gpio-0.dtsi"
164 gpio-controller@f000 {
165 compatible = "fsl,mpc8572-gpio";
168 L2: l2-cache-controller@20000 {
169 compatible = "fsl,mpc8572-l2-cache-controller";
171 cache-line-size = <32>; // 32 bytes
172 cache-size = <0x100000>; // L2,1M
176 /include/ "pq3-dma-0.dtsi"
177 /include/ "pq3-etsec1-0.dtsi"
178 /include/ "pq3-etsec1-timer-0.dtsi"
184 /include/ "pq3-etsec1-1.dtsi"
185 /include/ "pq3-etsec1-2.dtsi"
186 /include/ "pq3-etsec1-3.dtsi"
187 /include/ "pq3-sec3.0-0.dtsi"
188 /include/ "pq3-mpic.dtsi"
189 /include/ "pq3-mpic-timer-B.dtsi"
191 global-utilities@e0000 {
192 compatible = "fsl,mpc8572-guts";
194 fsl,has-rstcr;
197 /include/ "pq3-power.dtsi"