Lines Matching +full:1 +full:a0

31 	subu		t2, linesize, 1	;	\
34 	addiu		t1, t1, -1	;	\
59 #define CP0_BRCM_MODE		$22, 1
63 #define CP0_ICACHE_DATA_LO	$28, 1
67 #define CP0_ICACHE_DATA_HI	$29, 1
70 #define CP0_BRCM_MODE_Luc_MASK		(1 << 11)
71 #define	CP0_BRCM_CONFIG0_CWF_MASK	(1 << 20)
72 #define	CP0_BRCM_CONFIG0_TSE_MASK	(1 << 19)
73 #define CP0_BRCM_MODE_SET_MASK		(1 << 7)
95 #define BRCM_ZSC_CONFIG_LMB1En			1 << (15)
96 #define BRCM_ZSC_CONFIG_LMB0En			1 << (14)
113  * Trashes:	v0, v1, a0, t0
122 	mfc0	a0, CP0_CONFIG, 1
123 	move	t0, a0
130 	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
134 	srl	a0, a0, IS_SHIFT
135 	and	a0, a0, IS_MASK
140 	sllv	v0, v0, a0
150 	move	a0, t0
152 	srl	a0, a0, IL_SHIFT
153 	and	a0, a0, IL_MASK
155 	beqz	a0, no_i_cache
158 	/* line size = 2 ^ (IL+1) */
160 	addi	a0, a0, 1
161 	li	v1, 1
162 	sll	v1, v1, a0
168 	sll	v0, v0, a0
178 	move	a0, t0
180 	srl	a0, a0, IA_SHIFT
181 	and	a0, a0, IA_MASK
182 	addi	a0, a0, 0x1
188 	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
190 	b	1f
196 1:
208  * Trashes:	v0, v1, a0, t0
215 	mfc0	a0, CP0_CONFIG, 1
216 	move	t0, a0
223 	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
227 	srl	a0, a0, DS_SHIFT
228 	and	a0, a0, DS_MASK
233 	sllv	v0, v0, a0
242 	move	a0, t0
244 	srl	a0, a0, DL_SHIFT
245 	and	a0, a0, DL_MASK
247 	beqz	a0, no_d_cache
250 	/* line size = 2 ^ (IL+1) */
252 	addi	a0, a0, 1
253 	li	v1, 1
254 	sll	v1, v1, a0
260 	sll	v0, v0, a0
269 	move	a0, t0
271 	srl	a0, a0, DA_SHIFT
272 	and	a0, a0, DA_MASK
273 	addi	a0, a0, 0x1
279 	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
282 	b	1f
288 1:
324  * Trashes:	a0, v0, v1, t0, t1, t2, t8
354 	/* run uncached in kseg 1 */
355 	la	k0, 1f
360 1:
375 	li	a0, KSEG0
376 	cacheop(a0, v0, v1, Index_Store_Tag_I)
381 	la	k0, 1f
387 1:
396 	li	a0, KSEG0
397 	cacheop(a0, v0, v1, Index_Store_Tag_D)
426 	mfc0	t0, CP0_CACHEERR, 1
429 	mtc0	t0, CP0_CACHEERR, 1
521  * Arguments:	set clock ratio specified by a0
524  * Trashes:	v0, v1, a0, a1
537 	or	t0, t0, a0
578  * Arguments:	a0=0 disable llmb, a0=1 enables llmb
597 	beqz	a0, svlmb
620  * Trashes:	v0,v1,a0,a1,t8
636 	li	a0, 1
653 	 *set clock ratio by setting 1 to 'set'
656 	li	a0, 0
724 	/* save return address and A0 */
726 	move	t5, a0
739 	move 	a0, t5