99 	u32 pll;  in ar71xx_clocks_init()  local
105 	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);  in ar71xx_clocks_init()
107 	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;  in ar71xx_clocks_init()
110 	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;  in ar71xx_clocks_init()
113 	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;  in ar71xx_clocks_init()
116 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;  in ar71xx_clocks_init()
127 	u32 pll;  in ar724x_clocks_init()  local
131 	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);  in ar724x_clocks_init()
133 	mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);  in ar724x_clocks_init()
134 	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;  in ar724x_clocks_init()
136 	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;  in ar724x_clocks_init()
137 	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;  in ar724x_clocks_init()
238 	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;  in ar934x_clocks_init()  local
253 	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);  in ar934x_clocks_init()
254 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {  in ar934x_clocks_init()
255 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &  in ar934x_clocks_init()
257 		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);  in ar934x_clocks_init()
258 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &  in ar934x_clocks_init()
260 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;  in ar934x_clocks_init()
261 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
265 		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);  in ar934x_clocks_init()
266 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in ar934x_clocks_init()
268 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
270 		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &  in ar934x_clocks_init()
272 		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in ar934x_clocks_init()
280 	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);  in ar934x_clocks_init()
281 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {  in ar934x_clocks_init()
282 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &  in ar934x_clocks_init()
284 		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);  in ar934x_clocks_init()
285 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &  in ar934x_clocks_init()
287 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;  in ar934x_clocks_init()
288 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
292 		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);  in ar934x_clocks_init()
293 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in ar934x_clocks_init()
295 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
297 		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &  in ar934x_clocks_init()
299 		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in ar934x_clocks_init()
356 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;  in qca953x_clocks_init()  local
368 	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);  in qca953x_clocks_init()
369 	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in qca953x_clocks_init()
371 	ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca953x_clocks_init()
373 	nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &  in qca953x_clocks_init()
375 	frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in qca953x_clocks_init()
382 	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);  in qca953x_clocks_init()
383 	out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in qca953x_clocks_init()
385 	ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca953x_clocks_init()
387 	nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &  in qca953x_clocks_init()
389 	frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in qca953x_clocks_init()
439 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;  in qca955x_clocks_init()  local
451 	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);  in qca955x_clocks_init()
452 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in qca955x_clocks_init()
454 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
456 	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &  in qca955x_clocks_init()
458 	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in qca955x_clocks_init()
465 	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);  in qca955x_clocks_init()
466 	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in qca955x_clocks_init()
468 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
470 	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &  in qca955x_clocks_init()
472 	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in qca955x_clocks_init()
522 	u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;  in qca956x_clocks_init()  local
544 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);  in qca956x_clocks_init()
545 	out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in qca956x_clocks_init()
547 	ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca956x_clocks_init()
550 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);  in qca956x_clocks_init()
551 	nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &  in qca956x_clocks_init()
553 	hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &  in qca956x_clocks_init()
555 	lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &  in qca956x_clocks_init()
563 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);  in qca956x_clocks_init()
564 	out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in qca956x_clocks_init()
566 	ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca956x_clocks_init()
568 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);  in qca956x_clocks_init()
569 	nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &  in qca956x_clocks_init()
571 	hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &  in qca956x_clocks_init()
573 	lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &  in qca956x_clocks_init()
629 		pr_err("%pOF: can't map pll registers\n", np);  in ath79_clocks_init_dt()
633 	if (of_device_is_compatible(np, "qca,ar7100-pll"))  in ath79_clocks_init_dt()
635 	else if (of_device_is_compatible(np, "qca,ar7240-pll") ||  in ath79_clocks_init_dt()
636 		 of_device_is_compatible(np, "qca,ar9130-pll"))  in ath79_clocks_init_dt()
638 	else if (of_device_is_compatible(np, "qca,ar9330-pll"))  in ath79_clocks_init_dt()
640 	else if (of_device_is_compatible(np, "qca,ar9340-pll"))  in ath79_clocks_init_dt()
642 	else if (of_device_is_compatible(np, "qca,qca9530-pll"))  in ath79_clocks_init_dt()
644 	else if (of_device_is_compatible(np, "qca,qca9550-pll"))  in ath79_clocks_init_dt()
646 	else if (of_device_is_compatible(np, "qca,qca9560-pll"))  in ath79_clocks_init_dt()
666 CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
667 CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
668 CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
669 CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
670 CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
671 CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
672 CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
673 CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);