Lines Matching full:via
3 * 6522 Versatile Interface Adapter (VIA)
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
117 * correspond to a VIA work-alike named 'EVR'. */
132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
185 * right bit in the VIA chip (6522 Versatile Interface Adapter).
194 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
195 /* Note: 15 VIA regs, 8 RBV regs */
197 #define vBufB 0x0000 /* [VIA/RBV] Register B */
198 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
199 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
200 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
201 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
202 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
203 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
204 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
205 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
206 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
207 #define vSR 0x1400 /* [VIA only] Shift register. */
208 #define vACR 0x1600 /* [VIA only] Auxiliary control register. */
209 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */
213 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
214 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
215 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
217 /* The RBV only decodes the bottom eight address lines; the VIA doesn't
226 #define rBufB 0x0000 /* [VIA/RBV] Register B */
229 #define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
233 #define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
234 #define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */