Lines Matching +full:tx +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-j784s4.dtsi"
15 compatible = "ti,j784s4-evm", "ti,j784s4";
19 stdout-path = "serial2:115200n8";
36 bootph-all;
42 reserved_memory: reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
49 no-map;
52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
53 compatible = "shared-dma-pool";
55 no-map;
58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
59 compatible = "shared-dma-pool";
61 no-map;
64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
65 compatible = "shared-dma-pool";
67 no-map;
70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
71 compatible = "shared-dma-pool";
73 no-map;
76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
77 compatible = "shared-dma-pool";
79 no-map;
82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
83 compatible = "shared-dma-pool";
85 no-map;
88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
89 compatible = "shared-dma-pool";
91 no-map;
94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
95 compatible = "shared-dma-pool";
97 no-map;
100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
101 compatible = "shared-dma-pool";
103 no-map;
106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
107 compatible = "shared-dma-pool";
109 no-map;
112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
113 compatible = "shared-dma-pool";
115 no-map;
118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
119 compatible = "shared-dma-pool";
121 no-map;
124 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
125 compatible = "shared-dma-pool";
127 no-map;
130 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
131 compatible = "shared-dma-pool";
133 no-map;
136 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
137 compatible = "shared-dma-pool";
139 no-map;
142 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
143 compatible = "shared-dma-pool";
145 no-map;
148 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
149 compatible = "shared-dma-pool";
151 no-map;
154 c71_0_memory_region: c71-memory@a8100000 {
155 compatible = "shared-dma-pool";
157 no-map;
160 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
161 compatible = "shared-dma-pool";
163 no-map;
166 c71_1_memory_region: c71-memory@a9100000 {
167 compatible = "shared-dma-pool";
169 no-map;
172 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
173 compatible = "shared-dma-pool";
175 no-map;
178 c71_2_memory_region: c71-memory@aa100000 {
179 compatible = "shared-dma-pool";
181 no-map;
184 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
185 compatible = "shared-dma-pool";
187 no-map;
190 c71_3_memory_region: c71-memory@ab100000 {
191 compatible = "shared-dma-pool";
193 no-map;
197 evm_12v0: regulator-evm12v0 {
199 compatible = "regulator-fixed";
200 regulator-name = "evm_12v0";
201 regulator-min-microvolt = <12000000>;
202 regulator-max-microvolt = <12000000>;
203 regulator-always-on;
204 regulator-boot-on;
207 vsys_3v3: regulator-vsys3v3 {
209 compatible = "regulator-fixed";
210 regulator-name = "vsys_3v3";
211 regulator-min-microvolt = <3300000>;
212 regulator-max-microvolt = <3300000>;
213 vin-supply = <&evm_12v0>;
214 regulator-always-on;
215 regulator-boot-on;
218 vsys_5v0: regulator-vsys5v0 {
220 compatible = "regulator-fixed";
221 regulator-name = "vsys_5v0";
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5000000>;
224 vin-supply = <&evm_12v0>;
225 regulator-always-on;
226 regulator-boot-on;
229 vdd_mmc1: regulator-sd {
231 compatible = "regulator-fixed";
232 regulator-name = "vdd_mmc1";
233 regulator-min-microvolt = <3300000>;
234 regulator-max-microvolt = <3300000>;
235 regulator-boot-on;
236 enable-active-high;
237 vin-supply = <&vsys_3v3>;
241 vdd_sd_dv: regulator-TLV71033 {
243 compatible = "regulator-gpio";
244 regulator-name = "tlv71033";
245 pinctrl-names = "default";
246 pinctrl-0 = <&vdd_sd_dv_pins_default>;
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-boot-on;
250 vin-supply = <&vsys_5v0>;
256 dp0_pwr_3v3: regulator-dp0-prw {
257 compatible = "regulator-fixed";
258 regulator-name = "dp0-pwr";
259 regulator-min-microvolt = <3300000>;
260 regulator-max-microvolt = <3300000>;
262 enable-active-high;
265 dp0: connector-dp0 {
266 compatible = "dp-connector";
268 type = "full-size";
269 dp-pwr-supply = <&dp0_pwr_3v3>;
273 remote-endpoint = <&dp0_out>;
278 transceiver0: can-phy0 {
280 #phy-cells = <0>;
281 max-bitrate = <5000000>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
284 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>;
287 transceiver1: can-phy1 {
289 #phy-cells = <0>;
290 max-bitrate = <5000000>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
293 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
296 transceiver2: can-phy2 {
299 #phy-cells = <0>;
300 max-bitrate = <5000000>;
303 transceiver3: can-phy3 {
305 #phy-cells = <0>;
306 max-bitrate = <5000000>;
307 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
308 mux-states = <&mux1 1>;
311 mux1: mux-controller {
312 compatible = "gpio-mux";
313 #mux-state-cells = <1>;
314 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>;
315 idle-state = <1>;
319 compatible = "ti,j7200-cpb-audio";
320 model = "j784s4-cpb";
322 ti,cpb-mcasp = <&mcasp0>;
323 ti,cpb-codec = <&pcm3168a_1>;
327 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000",
328 "cpb-codec-scki", "cpb-codec-scki-48000";
337 bootph-all;
338 main_cpsw2g_default_pins: main-cpsw2g-default-pins {
339 pinctrl-single,pins = <
355 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
356 pinctrl-single,pins = <
362 main_uart8_pins_default: main-uart8-default-pins {
363 bootph-all;
364 pinctrl-single,pins = <
372 main_i2c0_pins_default: main-i2c0-default-pins {
373 pinctrl-single,pins = <
379 main_i2c5_pins_default: main-i2c5-default-pins {
380 pinctrl-single,pins = <
386 main_mmc1_pins_default: main-mmc1-default-pins {
387 bootph-all;
388 pinctrl-single,pins = <
400 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
401 pinctrl-single,pins = <
406 dp0_pins_default: dp0-default-pins {
407 pinctrl-single,pins = <
412 main_i2c4_pins_default: main-i2c4-default-pins {
413 pinctrl-single,pins = <
419 main_mcan4_pins_default: main-mcan4-default-pins {
420 pinctrl-single,pins = <
426 main_mcan16_pins_default: main-mcan16-default-pins {
427 pinctrl-single,pins = <
433 main_usbss0_pins_default: main-usbss0-default-pins {
434 bootph-all;
435 pinctrl-single,pins = <
440 main_i2c3_pins_default: main-i2c3-default-pins {
441 pinctrl-single,pins = <
447 main_mcasp0_pins_default: main-mcasp0-default-pins {
448 pinctrl-single,pins = <
456 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
457 pinctrl-single,pins = <
464 bootph-all;
465 wkup_uart0_pins_default: wkup-uart0-default-pins {
466 bootph-all;
467 pinctrl-single,pins = <
473 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
474 bootph-all;
475 pinctrl-single,pins = <
481 mcu_uart0_pins_default: mcu-uart0-default-pins {
482 bootph-all;
483 pinctrl-single,pins = <
491 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
492 pinctrl-single,pins = <
508 mcu_mdio_pins_default: mcu-mdio-default-pins {
509 pinctrl-single,pins = <
515 mcu_adc0_pins_default: mcu-adc0-default-pins {
516 pinctrl-single,pins = <
528 mcu_adc1_pins_default: mcu-adc1-default-pins {
529 pinctrl-single,pins = <
541 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
542 pinctrl-single,pins = <
548 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
549 pinctrl-single,pins = <
555 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
556 pinctrl-single,pins = <
561 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
562 pinctrl-single,pins = <
571 pmic_irq_pins_default: pmic-irq-default-pins {
572 pinctrl-single,pins = <
580 bootph-all;
581 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
582 bootph-all;
583 pinctrl-single,pins = <
600 bootph-all;
601 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
602 bootph-all;
603 pinctrl-single,pins = <
609 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
610 bootph-all;
611 pinctrl-single,pins = <
627 pinctrl-names = "default";
628 pinctrl-0 = <&wkup_uart0_pins_default>;
632 bootph-all;
634 pinctrl-names = "default";
635 pinctrl-0 = <&wkup_i2c0_pins_default>;
636 clock-frequency = <400000>;
639 /* CAV24C256WE-GT3 */
645 compatible = "ti,tps6594-q1";
647 system-power-controller;
648 pinctrl-names = "default";
649 pinctrl-0 = <&pmic_irq_pins_default>;
650 interrupt-parent = <&wkup_gpio0>;
652 gpio-controller;
653 #gpio-cells = <2>;
654 ti,primary-pmic;
655 buck12-supply = <&vsys_3v3>;
656 buck3-supply = <&vsys_3v3>;
657 buck4-supply = <&vsys_3v3>;
658 buck5-supply = <&vsys_3v3>;
659 ldo1-supply = <&vsys_3v3>;
660 ldo2-supply = <&vsys_3v3>;
661 ldo3-supply = <&vsys_3v3>;
662 ldo4-supply = <&vsys_3v3>;
666 regulator-name = "vdd_ddr_1v1";
667 regulator-min-microvolt = <1100000>;
668 regulator-max-microvolt = <1100000>;
669 regulator-boot-on;
670 regulator-always-on;
674 regulator-name = "vdd_ram_0v85";
675 regulator-min-microvolt = <850000>;
676 regulator-max-microvolt = <850000>;
677 regulator-boot-on;
678 regulator-always-on;
682 regulator-name = "vdd_io_1v8";
683 regulator-min-microvolt = <1800000>;
684 regulator-max-microvolt = <1800000>;
685 regulator-boot-on;
686 regulator-always-on;
690 regulator-name = "vdd_mcu_0v85";
691 regulator-min-microvolt = <850000>;
692 regulator-max-microvolt = <850000>;
693 regulator-boot-on;
694 regulator-always-on;
698 regulator-name = "vdd_mcuio_1v8";
699 regulator-min-microvolt = <1800000>;
700 regulator-max-microvolt = <1800000>;
701 regulator-boot-on;
702 regulator-always-on;
706 regulator-name = "vdd_mcuio_3v3";
707 regulator-min-microvolt = <3300000>;
708 regulator-max-microvolt = <3300000>;
709 regulator-boot-on;
710 regulator-always-on;
714 regulator-name = "vds_dll_0v8";
715 regulator-min-microvolt = <800000>;
716 regulator-max-microvolt = <800000>;
717 regulator-boot-on;
718 regulator-always-on;
722 regulator-name = "vda_mcu_1v8";
723 regulator-min-microvolt = <1800000>;
724 regulator-max-microvolt = <1800000>;
725 regulator-boot-on;
726 regulator-always-on;
734 bootph-pre-ram;
735 regulator-name = "VDD_CPU_AVS";
736 regulator-min-microvolt = <750000>;
737 regulator-max-microvolt = <1330000>;
738 regulator-boot-on;
739 regulator-always-on;
745 regulator-name = "VDD_CORE_0V8";
746 regulator-min-microvolt = <760000>;
747 regulator-max-microvolt = <840000>;
748 regulator-boot-on;
749 regulator-always-on;
754 bootph-all;
756 pinctrl-names = "default";
757 pinctrl-0 = <&mcu_uart0_pins_default>;
761 bootph-all;
763 pinctrl-names = "default";
764 pinctrl-0 = <&main_uart8_pins_default>;
772 bootph-all;
777 bootph-all;
779 pinctrl-names = "default";
780 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
783 bootph-all;
784 compatible = "jedec,spi-nor";
786 spi-tx-bus-width = <8>;
787 spi-rx-bus-width = <8>;
788 spi-max-frequency = <25000000>;
789 cdns,tshsl-ns = <60>;
790 cdns,tsd2d-ns = <60>;
791 cdns,tchsh-ns = <60>;
792 cdns,tslch-ns = <60>;
793 cdns,read-delay = <4>;
796 compatible = "fixed-partitions";
797 #address-cells = <1>;
798 #size-cells = <1>;
811 label = "ospi.u-boot";
831 bootph-all;
840 bootph-all;
842 pinctrl-names = "default";
843 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
846 bootph-all;
847 compatible = "jedec,spi-nor";
849 spi-tx-bus-width = <1>;
850 spi-rx-bus-width = <4>;
851 spi-max-frequency = <40000000>;
852 cdns,tshsl-ns = <60>;
853 cdns,tsd2d-ns = <60>;
854 cdns,tchsh-ns = <60>;
855 cdns,tslch-ns = <60>;
856 cdns,read-delay = <2>;
859 compatible = "fixed-partitions";
860 #address-cells = <1>;
861 #size-cells = <1>;
874 label = "qspi.u-boot";
894 bootph-all;
905 pinctrl-names = "default";
906 pinctrl-0 = <&main_i2c0_pins_default>;
908 clock-frequency = <400000>;
913 gpio-controller;
914 #gpio-cells = <2>;
915 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
921 p12-hog {
922 /* P12 - AUDIO_MUX_SEL */
923 gpio-hog;
925 output-low;
926 line-name = "AUDIO_MUX_SEL";
933 gpio-controller;
934 #gpio-cells = <2>;
935 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
944 p13-hog {
945 /* P13 - CANUART_MUX_SEL0 */
946 gpio-hog;
948 output-high;
949 line-name = "CANUART_MUX_SEL0";
952 p15-hog {
953 /* P15 - CANUART_MUX1_SEL1 */
954 gpio-hog;
956 output-high;
957 line-name = "CANUART_MUX1_SEL1";
963 pinctrl-names = "default";
964 pinctrl-0 = <&main_i2c5_pins_default>;
965 clock-frequency = <400000>;
971 gpio-controller;
972 #gpio-cells = <2>;
973 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0",
981 bootph-all;
984 non-removable;
985 ti,driver-strength-ohm = <50>;
986 disable-wp;
990 bootph-all;
993 pinctrl-0 = <&main_mmc1_pins_default>;
994 pinctrl-names = "default";
995 disable-wp;
996 vmmc-supply = <&vdd_mmc1>;
997 vqmmc-supply = <&vdd_sd_dv>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&mcu_cpsw_pins_default>;
1011 pinctrl-names = "default";
1012 pinctrl-0 = <&mcu_mdio_pins_default>;
1014 mcu_phy0: ethernet-phy@0 {
1016 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
1017 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1018 ti,min-output-impedance;
1024 phy-mode = "rgmii-rxid";
1025 phy-handle = <&mcu_phy0>;
1029 pinctrl-names = "default";
1030 pinctrl-0 = <&main_cpsw2g_default_pins>;
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
1039 main_cpsw1_phy0: ethernet-phy@0 {
1041 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
1042 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1043 ti,min-output-impedance;
1048 phy-mode = "rgmii-rxid";
1049 phy-handle = <&main_cpsw1_phy0>;
1057 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
1058 ti,mbox-rx = <0 0 0>;
1059 ti,mbox-tx = <1 0 0>;
1062 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
1063 ti,mbox-rx = <2 0 0>;
1064 ti,mbox-tx = <3 0 0>;
1072 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
1073 ti,mbox-rx = <0 0 0>;
1074 ti,mbox-tx = <1 0 0>;
1077 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
1078 ti,mbox-rx = <2 0 0>;
1079 ti,mbox-tx = <3 0 0>;
1087 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
1088 ti,mbox-rx = <0 0 0>;
1089 ti,mbox-tx = <1 0 0>;
1092 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
1093 ti,mbox-rx = <2 0 0>;
1094 ti,mbox-tx = <3 0 0>;
1102 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
1103 ti,mbox-rx = <0 0 0>;
1104 ti,mbox-tx = <1 0 0>;
1107 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
1108 ti,mbox-rx = <2 0 0>;
1109 ti,mbox-tx = <3 0 0>;
1117 mbox_c71_0: mbox-c71-0 {
1118 ti,mbox-rx = <0 0 0>;
1119 ti,mbox-tx = <1 0 0>;
1122 mbox_c71_1: mbox-c71-1 {
1123 ti,mbox-rx = <2 0 0>;
1124 ti,mbox-tx = <3 0 0>;
1132 mbox_c71_2: mbox-c71-2 {
1133 ti,mbox-rx = <0 0 0>;
1134 ti,mbox-tx = <1 0 0>;
1137 mbox_c71_3: mbox-c71-3 {
1138 ti,mbox-rx = <2 0 0>;
1139 ti,mbox-tx = <3 0 0>;
1146 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1153 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1158 ti,cluster-mode = <0>;
1162 ti,cluster-mode = <0>;
1166 ti,cluster-mode = <0>;
1213 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1220 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1227 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1234 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1241 memory-region = <&main_r5fss2_core0_dma_memory_region>,
1248 memory-region = <&main_r5fss2_core1_dma_memory_region>,
1255 memory-region = <&c71_0_dma_memory_region>,
1262 memory-region = <&c71_1_dma_memory_region>,
1269 memory-region = <&c71_2_dma_memory_region>,
1276 memory-region = <&c71_3_dma_memory_region>,
1281 pinctrl-0 = <&mcu_adc0_pins_default>;
1282 pinctrl-names = "default";
1285 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1290 pinctrl-0 = <&mcu_adc1_pins_default>;
1291 pinctrl-names = "default";
1294 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1300 clock-frequency = <100000000>;
1305 assigned-clocks = <&k3_clks 218 2>,
1309 assigned-clock-parents = <&k3_clks 218 3>,
1320 cdns,num-lanes = <2>;
1321 #phy-cells = <0>;
1322 cdns,phy-type = <PHY_TYPE_PCIE>;
1328 cdns,num-lanes = <1>;
1329 #phy-cells = <0>;
1330 cdns,phy-type = <PHY_TYPE_USB3>;
1340 idle-states = <0>; /* USB0 to SERDES lane 3 */
1345 pinctrl-0 = <&main_usbss0_pins_default>;
1346 pinctrl-names = "default";
1347 ti,vbus-divider;
1352 maximum-speed = "super-speed";
1354 phy-names = "cdns3,usb3-phy";
1365 cdns,num-lanes = <4>;
1366 #phy-cells = <0>;
1367 cdns,phy-type = <PHY_TYPE_DP>;
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&dp0_pins_default>;
1378 phy-names = "dpphy";
1385 remote-endpoint = <&dp0_in>;
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&main_i2c4_pins_default>;
1394 clock-frequency = <400000>;
1399 gpio-controller;
1400 #gpio-cells = <2>;
1409 remote-endpoint = <&dpi0_out>;
1417 remote-endpoint = <&dp0_connector_in>;
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&mcu_mcan0_pins_default>;
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&mcu_mcan1_pins_default>;
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&main_mcan16_pins_default>;
1445 pinctrl-names = "default";
1446 pinctrl-0 = <&main_mcan4_pins_default>;
1452 num-lanes = <2>;
1453 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
1455 phy-names = "pcie-phy";
1463 cdns,num-lanes = <4>;
1464 #phy-cells = <0>;
1465 cdns,phy-type = <PHY_TYPE_PCIE>;
1477 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
1479 phy-names = "pcie-phy";
1484 pinctrl-names = "default";
1485 pinctrl-0 = <&audio_ext_refclk1_pins_default>;
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&main_i2c3_pins_default>;
1492 clock-frequency = <400000>;
1497 gpio-controller;
1498 #gpio-cells = <2>;
1501 pcm3168a_1: audio-codec@44 {
1504 #sound-dai-cells = <1>;
1505 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
1507 clock-names = "scki";
1508 VDD1-supply = <&vsys_3v3>;
1509 VDD2-supply = <&vsys_3v3>;
1510 VCCAD1-supply = <&vsys_5v0>;
1511 VCCAD2-supply = <&vsys_5v0>;
1512 VCCDA1-supply = <&vsys_5v0>;
1513 VCCDA2-supply = <&vsys_5v0>;
1519 #sound-dai-cells = <0>;
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&main_mcasp0_pins_default>;
1522 op-mode = <0>; /* MCASP_IIS_MODE */
1523 tdm-slots = <2>;
1524 auxclk-fs-ratio = <256>;
1525 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */