Lines Matching +full:1 +full:- +full:9 +full:a +full:- +full:f
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 eth1_mdio_pins_a: eth1-mdio-0 {
11 pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
12 bias-disable;
13 drive-push-pull;
14 slew-rate = <2>;
17 pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */
18 bias-disable;
19 drive-push-pull;
20 slew-rate = <0>;
24 eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
26 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
27 <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
31 eth1_rgmii_pins_a: eth1-rgmii-0 {
33 pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
34 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
37 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
38 bias-disable;
39 drive-push-pull;
40 slew-rate = <3>;
41 st,io-sync = "data on both edges";
44 pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
46 bias-disable;
47 drive-push-pull;
48 slew-rate = <3>;
51 pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
55 <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
56 bias-disable;
57 st,io-sync = "data on both edges";
60 pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
61 bias-disable;
65 eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
67 pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
68 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
71 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
72 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
74 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
78 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
79 <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
83 eth1_rgmii_pins_b: eth1-rgmii-1 {
85 pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
86 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
89 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
90 bias-disable;
91 drive-push-pull;
92 slew-rate = <3>;
95 pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
97 <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */
98 <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */
99 bias-disable;
100 drive-push-pull;
101 slew-rate = <3>;
104 pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
108 <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
109 bias-disable;
112 pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
113 bias-disable;
117 eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 {
119 pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
120 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
123 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
124 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
126 <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */
127 <STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */
128 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
132 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
133 <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
137 eth2_rgmii_pins_a: eth2-rgmii-0 {
141 <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
144 bias-disable;
145 drive-push-pull;
146 slew-rate = <3>;
147 st,io-sync = "data on both edges";
150 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
151 <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
153 bias-disable;
154 drive-push-pull;
155 slew-rate = <3>;
159 bias-disable;
160 drive-push-pull;
161 slew-rate = <0>;
166 <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
169 bias-disable;
170 st,io-sync = "data on both edges";
173 pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
174 bias-disable;
178 eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
182 <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
185 <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */
186 <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
191 <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
194 <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
198 i2c2_pins_a: i2c2-0 {
202 bias-disable;
203 drive-open-drain;
204 slew-rate = <0>;
208 i2c2_sleep_pins_a: i2c2-sleep-0 {
215 ospi_port1_clk_pins_a: ospi-port1-clk-0 {
218 bias-disable;
219 drive-push-pull;
220 slew-rate = <2>;
224 ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 {
230 ospi_port1_cs0_pins_a: ospi-port1-cs0-0 {
233 bias-pull-up;
234 drive-push-pull;
235 slew-rate = <0>;
239 ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 {
245 ospi_port1_io03_pins_a: ospi-port1-io03-0 {
251 bias-disable;
252 drive-push-pull;
253 slew-rate = <0>;
257 ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 {
266 pcie_pins_a: pcie-0 {
269 bias-disable;
273 pcie_init_pins_a: pcie-init-0 {
276 output-low;
280 pcie_sleep_pins_a: pcie-sleep-0 {
286 pwm3_pins_a: pwm3-0 {
289 bias-pull-down;
290 drive-push-pull;
291 slew-rate = <0>;
295 pwm3_sleep_pins_a: pwm3-sleep-0 {
301 pwm8_pins_a: pwm8-0 {
305 bias-pull-down;
306 drive-push-pull;
307 slew-rate = <0>;
311 pwm8_sleep_pins_a: pwm8-sleep-0 {
318 pwm12_pins_a: pwm12-0 {
321 bias-pull-down;
322 drive-push-pull;
323 slew-rate = <0>;
327 pwm12_sleep_pins_a: pwm12-sleep-0 {
333 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
338 <STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */
340 slew-rate = <2>;
341 drive-push-pull;
342 bias-disable;
346 slew-rate = <3>;
347 drive-push-pull;
348 bias-disable;
352 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
357 <STM32_PINMUX('E', 1, AF10)>; /* SDMMC1_D3 */
358 slew-rate = <2>;
359 drive-push-pull;
360 bias-disable;
364 slew-rate = <3>;
365 drive-push-pull;
366 bias-disable;
370 slew-rate = <2>;
371 drive-open-drain;
372 bias-disable;
376 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
381 <STM32_PINMUX('E', 1, ANALOG)>, /* SDMMC1_D3 */
387 spi3_pins_a: spi3-0 {
391 drive-push-pull;
392 bias-disable;
393 slew-rate = <1>;
397 bias-disable;
401 spi3_sleep_pins_a: spi3-sleep-0 {
409 tim10_counter_pins_a: tim10-counter-0 {
411 pinmux = <STM32_PINMUX('B', 9, AF9)>; /* TIM10_CH1 */
412 bias-disable;
416 tim10_counter_sleep_pins_a: tim10-counter-sleep-0 {
418 pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* TIM10_CH1 */
419 bias-disable;
423 usart2_pins_a: usart2-0 {
425 pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
426 bias-disable;
427 drive-push-pull;
428 slew-rate = <0>;
431 pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
432 bias-disable;
436 usart2_idle_pins_a: usart2-idle-0 {
438 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
441 pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
442 bias-disable;
446 usart2_sleep_pins_a: usart2-sleep-0 {
448 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
449 <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
453 usart6_pins_a: usart6-0 {
455 pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */
457 bias-disable;
458 drive-push-pull;
459 slew-rate = <0>;
462 pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */
463 <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */
464 bias-pull-up;
468 usart6_idle_pins_a: usart6-idle-0 {
470 pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
471 <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */
475 bias-disable;
476 drive-push-pull;
477 slew-rate = <0>;
480 pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */
481 bias-pull-up;
485 usart6_sleep_pins_a: usart6-sleep-0 {
487 pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
489 <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */
490 <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */
496 i2c8_pins_a: i2c8-0 {
500 bias-disable;
501 drive-open-drain;
502 slew-rate = <0>;
506 i2c8_sleep_pins_a: i2c8-sleep-0 {
515 spi8_pins_a: spi8-0 {
519 drive-push-pull;
520 bias-disable;
521 slew-rate = <1>;
524 pinmux = <STM32_PINMUX('Z', 1, AF3)>; /* SPI8_MISO */
525 bias-disable;
529 spi8_sleep_pins_a: spi8-sleep-0 {
533 <STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */