Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
53 reg = <0x0 0x530000>;
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
60 compatible = "arm,cortex-a53";
61 reg = <0x0 0x530001>;
62 enable-method = "psci";
63 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
68 compatible = "arm,cortex-a53";
69 reg = <0x0 0x530002>;
70 enable-method = "psci";
71 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
76 compatible = "arm,cortex-a53";
77 reg = <0x0 0x530003>;
78 enable-method = "psci";
79 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
84 compatible = "arm,cortex-a53";
85 reg = <0x0 0x530100>;
86 enable-method = "psci";
87 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
92 compatible = "arm,cortex-a53";
93 reg = <0x0 0x530101>;
94 enable-method = "psci";
95 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
100 compatible = "arm,cortex-a53";
101 reg = <0x0 0x530102>;
102 enable-method = "psci";
103 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
108 compatible = "arm,cortex-a53";
109 reg = <0x0 0x530103>;
110 enable-method = "psci";
111 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
115 idle-states {
116 entry-method = "psci";
119 compatible = "arm,idle-state";
120 entry-latency-us = <1000>;
121 exit-latency-us = <700>;
122 min-residency-us = <2500>;
123 local-timer-stop;
124 arm,psci-suspend-param = <0x00010002>;
128 compatible = "arm,idle-state";
129 entry-latency-us = <1000>;
130 exit-latency-us = <1000>;
131 min-residency-us = <3000>;
132 local-timer-stop;
133 arm,psci-suspend-param = <0x01010003>;
137 psci {
138 compatible = "arm,psci-0.2";
143 compatible = "arm,armv8-timer";
155 compatible = "arm,cortex-a53-pmu";
164 interrupt-affinity = <&CPU0>,
175 gic: interrupt-controller@12001000 {
176 compatible = "arm,gic-400";
177 reg = <0 0x12001000 0 0x1000>,
178 <0 0x12002000 0 0x2000>,
179 <0 0x12004000 0 0x2000>,
180 <0 0x12006000 0 0x2000>;
181 #interrupt-cells = <3>;
182 interrupt-controller;
187 ap_clk: clock-controller@20000000 {
188 compatible = "sprd,sc9860-ap-clk";
189 reg = <0 0x20000000 0 0x400>;
190 clocks = <&ext_26m>, <&pll 0>,
191 <&pmu_gate 0>;
192 #clock-cells = <1>;
195 aon_prediv: aon-prediv@402d0000 {
196 compatible = "sprd,sc9860-aon-prediv";
197 reg = <0 0x402d0000 0 0x400>;
198 clocks = <&ext_26m>, <&pll 0>,
199 <&pmu_gate 0>;
200 #clock-cells = <1>;
204 aonsecure_clk: clock-controller@40880000 {
205 compatible = "sprd,sc9860-aonsecure-clk";
206 reg = <0 0x40880000 0 0x400>;
207 clocks = <&ext_26m>, <&pll 0>;
208 #clock-cells = <1>;
211 gpu_clk: clock-controller@60200000 {
212 compatible = "sprd,sc9860-gpu-clk";
213 reg = <0 0x60200000 0 0x400>;
214 clocks = <&pll 0>;
215 #clock-cells = <1>;
218 vsp_clk: clock-controller@61000000 {
219 compatible = "sprd,sc9860-vsp-clk";
220 reg = <0 0x61000000 0 0x400>;
221 clocks = <&ext_26m>, <&pll 0>;
222 #clock-cells = <1>;
225 cam_clk: clock-controller@62000000 {
226 compatible = "sprd,sc9860-cam-clk";
227 reg = <0 0x62000000 0 0x4000>;
228 clocks = <&ext_26m>, <&pll 0>;
229 #clock-cells = <1>;
232 disp_clk: clock-controller@63000000 {
233 compatible = "sprd,sc9860-disp-clk";
234 reg = <0 0x63000000 0 0x400>;
235 clocks = <&ext_26m>, <&pll 0>;
236 #clock-cells = <1>;
240 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
241 reg = <0 0x10001000 0 0x1000>;
243 clock-names = "apb_pclk";
244 out-ports {
247 remote-endpoint = <&etb_in>;
252 in-ports {
253 #address-cells = <1>;
254 #size-cells = <0>;
256 port@0 {
257 reg = <0>;
259 remote-endpoint =
267 remote-endpoint =
275 compatible = "arm,coresight-tmc", "arm,primecell";
276 reg = <0 0x10003000 0 0x1000>;
278 clock-names = "apb_pclk";
279 out-ports {
282 remote-endpoint =
290 compatible = "arm,coresight-stm", "arm,primecell";
291 reg = <0 0x10006000 0 0x1000>,
292 <0 0x01000000 0 0x180000>;
293 reg-names = "stm-base", "stm-stimulus-base";
295 clock-names = "apb_pclk";
296 out-ports {
299 remote-endpoint =
307 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
308 reg = <0 0x11001000 0 0x1000>;
310 clock-names = "apb_pclk";
311 out-ports {
314 remote-endpoint =
320 in-ports {
321 #address-cells = <1>;
322 #size-cells = <0>;
324 port@0 {
325 reg = <0>;
327 remote-endpoint = <&etm0_out>;
334 remote-endpoint = <&etm1_out>;
341 remote-endpoint = <&etm2_out>;
348 remote-endpoint = <&etm3_out>;
355 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
356 reg = <0 0x11002000 0 0x1000>;
358 clock-names = "apb_pclk";
359 out-ports {
362 remote-endpoint =
368 in-ports {
369 #address-cells = <1>;
370 #size-cells = <0>;
372 port@0 {
373 reg = <0>;
375 remote-endpoint = <&etm4_out>;
382 remote-endpoint = <&etm5_out>;
389 remote-endpoint = <&etm6_out>;
396 remote-endpoint = <&etm7_out>;
403 compatible = "arm,coresight-tmc", "arm,primecell";
404 reg = <0 0x11003000 0 0x1000>;
406 clock-names = "apb_pclk";
408 out-ports {
411 remote-endpoint =
417 in-ports {
420 remote-endpoint =
428 compatible = "arm,coresight-tmc", "arm,primecell";
429 reg = <0 0x11004000 0 0x1000>;
431 clock-names = "apb_pclk";
433 out-ports {
436 remote-endpoint =
442 in-ports {
445 remote-endpoint =
453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
454 reg = <0 0x11005000 0 0x1000>;
456 clock-names = "apb_pclk";
458 out-ports {
461 remote-endpoint =
467 in-ports {
468 #address-cells = <1>;
469 #size-cells = <0>;
471 port@0 {
472 reg = <0>;
474 remote-endpoint =
482 remote-endpoint =
490 compatible = "arm,coresight-etm4x", "arm,primecell";
491 reg = <0 0x11440000 0 0x1000>;
494 clock-names = "apb_pclk";
496 out-ports {
499 remote-endpoint =
507 compatible = "arm,coresight-etm4x", "arm,primecell";
508 reg = <0 0x11540000 0 0x1000>;
511 clock-names = "apb_pclk";
513 out-ports {
516 remote-endpoint =
524 compatible = "arm,coresight-etm4x", "arm,primecell";
525 reg = <0 0x11640000 0 0x1000>;
528 clock-names = "apb_pclk";
530 out-ports {
533 remote-endpoint =
541 compatible = "arm,coresight-etm4x", "arm,primecell";
542 reg = <0 0x11740000 0 0x1000>;
545 clock-names = "apb_pclk";
547 out-ports {
550 remote-endpoint =
558 compatible = "arm,coresight-etm4x", "arm,primecell";
559 reg = <0 0x11840000 0 0x1000>;
562 clock-names = "apb_pclk";
564 out-ports {
567 remote-endpoint =
575 compatible = "arm,coresight-etm4x", "arm,primecell";
576 reg = <0 0x11940000 0 0x1000>;
579 clock-names = "apb_pclk";
581 out-ports {
584 remote-endpoint =
592 compatible = "arm,coresight-etm4x", "arm,primecell";
593 reg = <0 0x11a40000 0 0x1000>;
596 clock-names = "apb_pclk";
598 out-ports {
601 remote-endpoint =
609 compatible = "arm,coresight-etm4x", "arm,primecell";
610 reg = <0 0x11b40000 0 0x1000>;
613 clock-names = "apb_pclk";
615 out-ports {
618 remote-endpoint =