Lines Matching +full:dcb +full:- +full:algorithm
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
26 enable-method = "psci";
30 compatible = "arm,cortex-a55";
33 next-level-cache = <&L3_CA55>;
34 enable-method = "psci";
38 compatible = "arm,cortex-a55";
41 next-level-cache = <&L3_CA55>;
42 enable-method = "psci";
46 compatible = "arm,cortex-a55";
49 next-level-cache = <&L3_CA55>;
50 enable-method = "psci";
53 L3_CA55: cache-controller-0 {
55 cache-unified;
56 cache-size = <0x100000>;
57 cache-level = <3>;
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
65 clock-frequency = <0>;
69 compatible = "arm,cortex-a55-pmu";
74 compatible = "arm,psci-1.0", "arm,psci-0.2";
79 compatible = "simple-bus";
80 #address-cells = <2>;
81 #size-cells = <2>;
85 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
91 interrupt-names = "eri", "rxi", "txi", "tei";
93 clock-names = "operation", "bus";
94 power-domains = <&cpg>;
99 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
105 interrupt-names = "eri", "rxi", "txi", "tei";
107 clock-names = "operation", "bus";
108 power-domains = <&cpg>;
113 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
119 interrupt-names = "eri", "rxi", "txi", "tei";
121 clock-names = "operation", "bus";
122 power-domains = <&cpg>;
127 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
133 interrupt-names = "eri", "rxi", "txi", "tei";
135 clock-names = "operation", "bus";
136 power-domains = <&cpg>;
141 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
147 interrupt-names = "eri", "rxi", "txi", "tei";
149 clock-names = "operation", "bus";
150 power-domains = <&cpg>;
155 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
161 interrupt-names = "eri", "rxi", "txi", "tei";
163 clock-names = "operation", "bus";
164 power-domains = <&cpg>;
169 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
173 clock-names = "pclk";
174 power-domains = <&cpg>;
179 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
183 clock-names = "pclk";
184 power-domains = <&cpg>;
189 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
193 clock-names = "pclk";
194 power-domains = <&cpg>;
199 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
203 clock-names = "pclk";
204 power-domains = <&cpg>;
209 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
213 clock-names = "pclk";
214 power-domains = <&cpg>;
219 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
223 clock-names = "pclk";
224 power-domains = <&cpg>;
229 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
235 interrupt-names = "eei", "rxi", "txi", "tei";
237 power-domains = <&cpg>;
238 #address-cells = <1>;
239 #size-cells = <0>;
244 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
250 interrupt-names = "eei", "rxi", "txi", "tei";
252 power-domains = <&cpg>;
253 #address-cells = <1>;
254 #size-cells = <0>;
259 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
265 interrupt-names = "eei", "rxi", "txi", "tei";
267 power-domains = <&cpg>;
268 #address-cells = <1>;
269 #size-cells = <0>;
274 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
275 "snps,dwmac-5.20";
296 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
297 "rx-queue-0", "rx-queue-1", "rx-queue-2",
298 "rx-queue-3", "rx-queue-4", "rx-queue-5",
299 "rx-queue-6", "rx-queue-7", "tx-queue-0",
300 "tx-queue-1", "tx-queue-2", "tx-queue-3",
301 "tx-queue-4", "tx-queue-5", "tx-queue-6",
302 "tx-queue-7";
306 clock-names = "stmmaceth", "pclk", "tx";
308 reset-names = "stmmaceth", "ahb";
309 power-domains = <&cpg>;
310 snps,multicast-filter-bins = <256>;
311 snps,perfect-filter-entries = <32>;
312 rx-fifo-depth = <8192>;
313 tx-fifo-depth = <8192>;
314 snps,fixed-burst;
315 snps,no-pbl-x8;
317 snps,axi-config = <&stmmac_axi_setup>;
318 snps,mtl-rx-config = <&mtl_rx_setup0>;
319 snps,mtl-tx-config = <&mtl_tx_setup0>;
325 compatible = "snps,dwmac-mdio";
326 #address-cells = <1>;
327 #size-cells = <0>;
330 mtl_rx_setup0: rx-queues-config {
331 snps,rx-queues-to-use = <8>;
332 snps,rx-sched-sp;
335 snps,dcb-algorithm;
337 snps,map-to-dma-channel = <0>;
341 snps,dcb-algorithm;
343 snps,map-to-dma-channel = <1>;
347 snps,dcb-algorithm;
349 snps,map-to-dma-channel = <2>;
353 snps,dcb-algorithm;
355 snps,map-to-dma-channel = <3>;
359 snps,dcb-algorithm;
361 snps,map-to-dma-channel = <4>;
365 snps,dcb-algorithm;
367 snps,map-to-dma-channel = <5>;
371 snps,dcb-algorithm;
373 snps,map-to-dma-channel = <6>;
377 snps,dcb-algorithm;
379 snps,map-to-dma-channel = <7>;
383 mtl_tx_setup0: tx-queues-config {
384 snps,tx-queues-to-use = <8>;
387 snps,dcb-algorithm;
391 snps,dcb-algorithm;
395 snps,dcb-algorithm;
399 snps,dcb-algorithm;
403 snps,dcb-algorithm;
407 snps,dcb-algorithm;
411 snps,dcb-algorithm;
415 snps,dcb-algorithm;
421 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
422 "snps,dwmac-5.20";
443 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
444 "rx-queue-0", "rx-queue-1", "rx-queue-2",
445 "rx-queue-3", "rx-queue-4", "rx-queue-5",
446 "rx-queue-6", "rx-queue-7", "tx-queue-0",
447 "tx-queue-1", "tx-queue-2", "tx-queue-3",
448 "tx-queue-4", "tx-queue-5", "tx-queue-6",
449 "tx-queue-7";
453 clock-names = "stmmaceth", "pclk", "tx";
455 reset-names = "stmmaceth", "ahb";
456 power-domains = <&cpg>;
457 snps,multicast-filter-bins = <256>;
458 snps,perfect-filter-entries = <32>;
459 rx-fifo-depth = <8192>;
460 tx-fifo-depth = <8192>;
461 snps,fixed-burst;
462 snps,no-pbl-x8;
464 snps,axi-config = <&stmmac_axi_setup>;
465 snps,mtl-rx-config = <&mtl_rx_setup1>;
466 snps,mtl-tx-config = <&mtl_tx_setup1>;
472 compatible = "snps,dwmac-mdio";
473 #address-cells = <1>;
474 #size-cells = <0>;
477 mtl_rx_setup1: rx-queues-config {
478 snps,rx-queues-to-use = <8>;
479 snps,rx-sched-sp;
482 snps,dcb-algorithm;
484 snps,map-to-dma-channel = <0>;
488 snps,dcb-algorithm;
490 snps,map-to-dma-channel = <1>;
494 snps,dcb-algorithm;
496 snps,map-to-dma-channel = <2>;
500 snps,dcb-algorithm;
502 snps,map-to-dma-channel = <3>;
506 snps,dcb-algorithm;
508 snps,map-to-dma-channel = <4>;
512 snps,dcb-algorithm;
514 snps,map-to-dma-channel = <5>;
518 snps,dcb-algorithm;
520 snps,map-to-dma-channel = <6>;
524 snps,dcb-algorithm;
526 snps,map-to-dma-channel = <7>;
530 mtl_tx_setup1: tx-queues-config {
531 snps,tx-queues-to-use = <8>;
534 snps,dcb-algorithm;
538 snps,dcb-algorithm;
542 snps,dcb-algorithm;
546 snps,dcb-algorithm;
550 snps,dcb-algorithm;
554 snps,dcb-algorithm;
558 snps,dcb-algorithm;
562 snps,dcb-algorithm;
568 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
569 "snps,dwmac-5.20";
590 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
591 "rx-queue-0", "rx-queue-1", "rx-queue-2",
592 "rx-queue-3", "rx-queue-4", "rx-queue-5",
593 "rx-queue-6", "rx-queue-7", "tx-queue-0",
594 "tx-queue-1", "tx-queue-2", "tx-queue-3",
595 "tx-queue-4", "tx-queue-5", "tx-queue-6",
596 "tx-queue-7";
600 clock-names = "stmmaceth", "pclk", "tx";
602 reset-names = "stmmaceth", "ahb";
603 power-domains = <&cpg>;
604 snps,multicast-filter-bins = <256>;
605 snps,perfect-filter-entries = <32>;
606 rx-fifo-depth = <8192>;
607 tx-fifo-depth = <8192>;
608 snps,fixed-burst;
609 snps,no-pbl-x8;
611 snps,axi-config = <&stmmac_axi_setup>;
612 snps,mtl-rx-config = <&mtl_rx_setup2>;
613 snps,mtl-tx-config = <&mtl_tx_setup2>;
619 compatible = "snps,dwmac-mdio";
620 #address-cells = <1>;
621 #size-cells = <0>;
624 mtl_rx_setup2: rx-queues-config {
625 snps,rx-queues-to-use = <8>;
626 snps,rx-sched-sp;
629 snps,dcb-algorithm;
631 snps,map-to-dma-channel = <0>;
635 snps,dcb-algorithm;
637 snps,map-to-dma-channel = <1>;
641 snps,dcb-algorithm;
643 snps,map-to-dma-channel = <2>;
647 snps,dcb-algorithm;
649 snps,map-to-dma-channel = <3>;
653 snps,dcb-algorithm;
655 snps,map-to-dma-channel = <4>;
659 snps,dcb-algorithm;
661 snps,map-to-dma-channel = <5>;
665 snps,dcb-algorithm;
667 snps,map-to-dma-channel = <6>;
671 snps,dcb-algorithm;
673 snps,map-to-dma-channel = <7>;
677 mtl_tx_setup2: tx-queues-config {
678 snps,tx-queues-to-use = <8>;
681 snps,dcb-algorithm;
685 snps,dcb-algorithm;
689 snps,dcb-algorithm;
693 snps,dcb-algorithm;
697 snps,dcb-algorithm;
701 snps,dcb-algorithm;
705 snps,dcb-algorithm;
709 snps,dcb-algorithm;
715 compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic";
721 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
723 reset-names = "rst", "crst";
724 power-domains = <&cpg>;
727 #address-cells = <1>;
728 #size-cells = <0>;
730 mii_conv0: mii-conv@0 {
735 mii_conv1: mii-conv@1 {
740 mii_conv2: mii-conv@2 {
745 mii_conv3: mii-conv@3 {
751 cpg: clock-controller@80280000 {
752 compatible = "renesas,r9a09g087-cpg-mssr";
756 clock-names = "extal";
757 #clock-cells = <2>;
758 #reset-cells = <1>;
759 #power-domain-cells = <0>;
763 compatible = "renesas,r9a09g087-pinctrl";
767 reg-names = "nsr", "srs", "srn";
769 gpio-controller;
770 #gpio-cells = <2>;
771 gpio-ranges = <&pinctrl 0 0 280>;
772 power-domains = <&cpg>;
775 gic: interrupt-controller@83000000 {
776 compatible = "arm,gic-v3";
779 #interrupt-cells = <3>;
780 #address-cells = <0>;
781 interrupt-controller;
786 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
795 interrupt-names = "adi", "gbadi", "gcadi",
799 clock-names = "adclk", "pclk";
800 power-domains = <&cpg>;
801 #address-cells = <1>;
802 #size-cells = <0>;
803 #io-channel-cells = <1>;
808 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
817 interrupt-names = "adi", "gbadi", "gcadi",
821 clock-names = "adclk", "pclk";
822 power-domains = <&cpg>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 #io-channel-cells = <1>;
830 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
839 interrupt-names = "adi", "gbadi", "gcadi",
843 clock-names = "adclk", "pclk";
844 power-domains = <&cpg>;
845 #address-cells = <1>;
846 #size-cells = <0>;
847 #io-channel-cells = <1>;
852 compatible = "generic-ohci";
857 phy-names = "usb";
858 power-domains = <&cpg>;
863 compatible = "generic-ehci";
868 phy-names = "usb";
870 power-domains = <&cpg>;
874 usb2_phy: usb-phy@92040200 {
875 compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077";
880 #phy-cells = <1>;
881 power-domains = <&cpg>;
886 compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077";
893 phy-names = "usb";
894 power-domains = <&cpg>;
899 compatible = "renesas,sdhi-r9a09g087",
900 "renesas,sdhi-r9a09g057";
906 clock-names = "aclk", "clkh";
907 power-domains = <&cpg>;
910 sdhi0_vqmmc: vqmmc-regulator {
911 regulator-name = "SDHI0-VQMMC";
912 regulator-min-microvolt = <1800000>;
913 regulator-max-microvolt = <3300000>;
919 compatible = "renesas,sdhi-r9a09g087",
920 "renesas,sdhi-r9a09g057";
926 clock-names = "aclk", "clkh";
927 power-domains = <&cpg>;
930 sdhi1_vqmmc: vqmmc-regulator {
931 regulator-name = "SDHI1-VQMMC";
932 regulator-min-microvolt = <1800000>;
933 regulator-max-microvolt = <3300000>;
939 stmmac_axi_setup: stmmac-axi-config {
947 compatible = "arm,armv8-timer";
953 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";