Lines Matching +full:gcc +full:- +full:msm8996
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
9 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
11 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
13 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
20 #include <dt-bindings/mailbox/qcom-ipcc.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/power/qcom,rpmhpd.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
38 xo_board: xo-board {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
48 bi_tcxo_div2: bi-tcxo-div2-clk {
49 #clock-cells = <0>;
50 compatible = "fixed-factor-clock";
52 clock-mult = <1>;
53 clock-div = <2>;
56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
57 #clock-cells = <0>;
58 compatible = "fixed-factor-clock";
60 clock-mult = <1>;
61 clock-div = <2>;
66 #address-cells = <2>;
67 #size-cells = <0>;
71 compatible = "arm,cortex-a510";
74 enable-method = "psci";
75 next-level-cache = <&l2_0>;
76 power-domains = <&cpu_pd0>;
77 power-domain-names = "psci";
78 qcom,freq-domain = <&cpufreq_hw 0>;
79 capacity-dmips-mhz = <1024>;
80 dynamic-power-coefficient = <100>;
81 #cooling-cells = <2>;
82 l2_0: l2-cache {
84 cache-level = <2>;
85 cache-unified;
86 next-level-cache = <&l3_0>;
87 l3_0: l3-cache {
89 cache-level = <3>;
90 cache-unified;
97 compatible = "arm,cortex-a510";
100 enable-method = "psci";
101 next-level-cache = <&l2_100>;
102 power-domains = <&cpu_pd1>;
103 power-domain-names = "psci";
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 capacity-dmips-mhz = <1024>;
106 dynamic-power-coefficient = <100>;
107 #cooling-cells = <2>;
108 l2_100: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&l3_0>;
118 compatible = "arm,cortex-a510";
121 enable-method = "psci";
122 next-level-cache = <&l2_200>;
123 power-domains = <&cpu_pd2>;
124 power-domain-names = "psci";
125 qcom,freq-domain = <&cpufreq_hw 0>;
126 capacity-dmips-mhz = <1024>;
127 dynamic-power-coefficient = <100>;
128 #cooling-cells = <2>;
129 l2_200: l2-cache {
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
139 compatible = "arm,cortex-a715";
142 enable-method = "psci";
143 next-level-cache = <&l2_300>;
144 power-domains = <&cpu_pd3>;
145 power-domain-names = "psci";
146 qcom,freq-domain = <&cpufreq_hw 1>;
147 capacity-dmips-mhz = <1792>;
148 dynamic-power-coefficient = <270>;
149 #cooling-cells = <2>;
150 l2_300: l2-cache {
152 cache-level = <2>;
153 cache-unified;
154 next-level-cache = <&l3_0>;
160 compatible = "arm,cortex-a715";
163 enable-method = "psci";
164 next-level-cache = <&l2_400>;
165 power-domains = <&cpu_pd4>;
166 power-domain-names = "psci";
167 qcom,freq-domain = <&cpufreq_hw 1>;
168 capacity-dmips-mhz = <1792>;
169 dynamic-power-coefficient = <270>;
170 #cooling-cells = <2>;
171 l2_400: l2-cache {
173 cache-level = <2>;
174 cache-unified;
175 next-level-cache = <&l3_0>;
181 compatible = "arm,cortex-a710";
184 enable-method = "psci";
185 next-level-cache = <&l2_500>;
186 power-domains = <&cpu_pd5>;
187 power-domain-names = "psci";
188 qcom,freq-domain = <&cpufreq_hw 1>;
189 capacity-dmips-mhz = <1792>;
190 dynamic-power-coefficient = <270>;
191 #cooling-cells = <2>;
192 l2_500: l2-cache {
194 cache-level = <2>;
195 cache-unified;
196 next-level-cache = <&l3_0>;
202 compatible = "arm,cortex-a710";
205 enable-method = "psci";
206 next-level-cache = <&l2_600>;
207 power-domains = <&cpu_pd6>;
208 power-domain-names = "psci";
209 qcom,freq-domain = <&cpufreq_hw 1>;
210 capacity-dmips-mhz = <1792>;
211 dynamic-power-coefficient = <270>;
212 #cooling-cells = <2>;
213 l2_600: l2-cache {
215 cache-level = <2>;
216 cache-unified;
217 next-level-cache = <&l3_0>;
223 compatible = "arm,cortex-x3";
226 enable-method = "psci";
227 next-level-cache = <&l2_700>;
228 power-domains = <&cpu_pd7>;
229 power-domain-names = "psci";
230 qcom,freq-domain = <&cpufreq_hw 2>;
231 capacity-dmips-mhz = <1894>;
232 dynamic-power-coefficient = <588>;
233 #cooling-cells = <2>;
234 l2_700: l2-cache {
236 cache-level = <2>;
237 cache-unified;
238 next-level-cache = <&l3_0>;
242 cpu-map {
278 idle-states {
279 entry-method = "psci";
281 little_cpu_sleep_0: cpu-sleep-0-0 {
282 compatible = "arm,idle-state";
283 idle-state-name = "silver-rail-power-collapse";
284 arm,psci-suspend-param = <0x40000004>;
285 entry-latency-us = <550>;
286 exit-latency-us = <750>;
287 min-residency-us = <6700>;
288 local-timer-stop;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "gold-rail-power-collapse";
294 arm,psci-suspend-param = <0x40000004>;
295 entry-latency-us = <600>;
296 exit-latency-us = <1300>;
297 min-residency-us = <8136>;
298 local-timer-stop;
301 prime_cpu_sleep_0: cpu-sleep-2-0 {
302 compatible = "arm,idle-state";
303 idle-state-name = "goldplus-rail-power-collapse";
304 arm,psci-suspend-param = <0x40000004>;
305 entry-latency-us = <500>;
306 exit-latency-us = <1350>;
307 min-residency-us = <7480>;
308 local-timer-stop;
312 domain-idle-states {
313 cluster_sleep_0: cluster-sleep-0 {
314 compatible = "domain-idle-state";
315 arm,psci-suspend-param = <0x41000044>;
316 entry-latency-us = <750>;
317 exit-latency-us = <2350>;
318 min-residency-us = <9144>;
321 cluster_sleep_1: cluster-sleep-1 {
322 compatible = "domain-idle-state";
323 arm,psci-suspend-param = <0x4100c344>;
324 entry-latency-us = <2800>;
325 exit-latency-us = <4400>;
326 min-residency-us = <10150>;
333 compatible = "qcom,scm-sm8550", "qcom,scm";
334 qcom,dload-mode = <&tcsr 0x19000>;
340 clk_virt: interconnect-0 {
341 compatible = "qcom,sm8550-clk-virt";
342 #interconnect-cells = <2>;
343 qcom,bcm-voters = <&apps_bcm_voter>;
346 mc_virt: interconnect-1 {
347 compatible = "qcom,sm8550-mc-virt";
348 #interconnect-cells = <2>;
349 qcom,bcm-voters = <&apps_bcm_voter>;
352 qup_opp_table_100mhz: opp-table-qup100mhz {
353 compatible = "operating-points-v2";
355 opp-75000000 {
356 opp-hz = /bits/ 64 <75000000>;
357 required-opps = <&rpmhpd_opp_low_svs>;
360 opp-100000000 {
361 opp-hz = /bits/ 64 <100000000>;
362 required-opps = <&rpmhpd_opp_svs>;
366 qup_opp_table_120mhz: opp-table-qup120mhz {
367 compatible = "operating-points-v2";
369 opp-75000000 {
370 opp-hz = /bits/ 64 <75000000>;
371 required-opps = <&rpmhpd_opp_low_svs>;
374 opp-120000000 {
375 opp-hz = /bits/ 64 <120000000>;
376 required-opps = <&rpmhpd_opp_svs>;
380 qup_opp_table_125mhz: opp-table-qup125mhz {
381 compatible = "operating-points-v2";
383 opp-75000000 {
384 opp-hz = /bits/ 64 <75000000>;
385 required-opps = <&rpmhpd_opp_low_svs>;
388 opp-125000000 {
389 opp-hz = /bits/ 64 <125000000>;
390 required-opps = <&rpmhpd_opp_svs>;
400 pmu-a510 {
401 compatible = "arm,cortex-a510-pmu";
405 pmu-a710 {
406 compatible = "arm,cortex-a710-pmu";
410 pmu-a715 {
411 compatible = "arm,cortex-a715-pmu";
415 pmu-x3 {
416 compatible = "arm,cortex-x3-pmu";
421 compatible = "arm,psci-1.0";
424 cpu_pd0: power-domain-cpu0 {
425 #power-domain-cells = <0>;
426 power-domains = <&cluster_pd>;
427 domain-idle-states = <&little_cpu_sleep_0>;
430 cpu_pd1: power-domain-cpu1 {
431 #power-domain-cells = <0>;
432 power-domains = <&cluster_pd>;
433 domain-idle-states = <&little_cpu_sleep_0>;
436 cpu_pd2: power-domain-cpu2 {
437 #power-domain-cells = <0>;
438 power-domains = <&cluster_pd>;
439 domain-idle-states = <&little_cpu_sleep_0>;
442 cpu_pd3: power-domain-cpu3 {
443 #power-domain-cells = <0>;
444 power-domains = <&cluster_pd>;
445 domain-idle-states = <&big_cpu_sleep_0>;
448 cpu_pd4: power-domain-cpu4 {
449 #power-domain-cells = <0>;
450 power-domains = <&cluster_pd>;
451 domain-idle-states = <&big_cpu_sleep_0>;
454 cpu_pd5: power-domain-cpu5 {
455 #power-domain-cells = <0>;
456 power-domains = <&cluster_pd>;
457 domain-idle-states = <&big_cpu_sleep_0>;
460 cpu_pd6: power-domain-cpu6 {
461 #power-domain-cells = <0>;
462 power-domains = <&cluster_pd>;
463 domain-idle-states = <&big_cpu_sleep_0>;
466 cpu_pd7: power-domain-cpu7 {
467 #power-domain-cells = <0>;
468 power-domains = <&cluster_pd>;
469 domain-idle-states = <&prime_cpu_sleep_0>;
472 cluster_pd: power-domain-cluster {
473 #power-domain-cells = <0>;
474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
478 reserved_memory: reserved-memory {
479 #address-cells = <2>;
480 #size-cells = <2>;
483 hyp_mem: hyp-region@80000000 {
485 no-map;
488 cpusys_vm_mem: cpusys-vm-region@80a00000 {
490 no-map;
493 hyp_tags_mem: hyp-tags-region@80e00000 {
495 no-map;
498 xbl_sc_mem: xbl-sc-region@d8100000 {
500 no-map;
503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
505 no-map;
509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
511 no-map;
514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
515 compatible = "qcom,cmd-db";
517 no-map;
521 aop_config_merged_mem: aop-config-merged-region@81c80000 {
523 no-map;
531 no-map;
534 adsp_mhi_mem: adsp-mhi-region@81f00000 {
536 no-map;
539 global_sync_mem: global-sync-region@82600000 {
541 no-map;
544 tz_stat_mem: tz-stat-region@82700000 {
546 no-map;
549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
551 no-map;
554 mpss_mem: mpss-region@8a800000 {
556 no-map;
559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
561 no-map;
564 ipa_fw_mem: ipa-fw-region@9b080000 {
566 no-map;
569 ipa_gsi_mem: ipa-gsi-region@9b090000 {
571 no-map;
574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
576 no-map;
579 spss_region_mem: spss-region@9b100000 {
581 no-map;
585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
587 no-map;
591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
593 no-map;
596 camera_mem: camera-region@9b300000 {
598 no-map;
601 video_mem: video-region@9bb00000 {
603 no-map;
606 cvp_mem: cvp-region@9c200000 {
608 no-map;
611 cdsp_mem: cdsp-region@9c900000 {
613 no-map;
616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
618 no-map;
621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
623 no-map;
626 adspslpi_mem: adspslpi-region@9ea00000 {
628 no-map;
635 rmtfs_mem: rmtfs-region@d4a80000 {
636 compatible = "qcom,rmtfs-mem";
638 no-map;
640 qcom,client-id = <1>;
644 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
646 no-map;
649 tz_reserved_mem: tz-reserved-region@d8000000 {
651 no-map;
654 cpucp_fw_mem: cpucp-fw-region@d8140000 {
656 no-map;
659 qtee_mem: qtee-region@d8300000 {
661 no-map;
664 ta_mem: ta-region@d8800000 {
666 no-map;
669 tz_tags_mem: tz-tags-region@e1200000 {
671 no-map;
674 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
676 no-map;
679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
681 no-map;
684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
686 no-map;
689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
691 no-map;
694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
696 no-map;
699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
701 no-map;
704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
706 no-map;
709 oem_vm_mem: oem-vm-region@f8400000 {
711 no-map;
714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
716 no-map;
719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
721 no-map;
724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
726 no-map;
729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
731 no-map;
735 smp2p-adsp {
738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
744 qcom,local-pid = <0>;
745 qcom,remote-pid = <2>;
747 smp2p_adsp_out: master-kernel {
748 qcom,entry-name = "master-kernel";
749 #qcom,smem-state-cells = <1>;
752 smp2p_adsp_in: slave-kernel {
753 qcom,entry-name = "slave-kernel";
754 interrupt-controller;
755 #interrupt-cells = <2>;
759 smp2p-cdsp {
762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
768 qcom,local-pid = <0>;
769 qcom,remote-pid = <5>;
771 smp2p_cdsp_out: master-kernel {
772 qcom,entry-name = "master-kernel";
773 #qcom,smem-state-cells = <1>;
776 smp2p_cdsp_in: slave-kernel {
777 qcom,entry-name = "slave-kernel";
778 interrupt-controller;
779 #interrupt-cells = <2>;
783 smp2p-modem {
786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
792 qcom,local-pid = <0>;
793 qcom,remote-pid = <1>;
795 smp2p_modem_out: master-kernel {
796 qcom,entry-name = "master-kernel";
797 #qcom,smem-state-cells = <1>;
800 smp2p_modem_in: slave-kernel {
801 qcom,entry-name = "slave-kernel";
802 interrupt-controller;
803 #interrupt-cells = <2>;
806 ipa_smp2p_out: ipa-ap-to-modem {
807 qcom,entry-name = "ipa";
808 #qcom,smem-state-cells = <1>;
811 ipa_smp2p_in: ipa-modem-to-ap {
812 qcom,entry-name = "ipa";
813 interrupt-controller;
814 #interrupt-cells = <2>;
819 compatible = "simple-bus";
821 dma-ranges = <0 0 0 0 0x10 0>;
823 #address-cells = <2>;
824 #size-cells = <2>;
826 gcc: clock-controller@100000 { label
827 compatible = "qcom,sm8550-gcc";
829 #clock-cells = <1>;
830 #reset-cells = <1>;
831 #power-domain-cells = <1>;
843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
846 interrupt-controller;
847 #interrupt-cells = <3>;
848 #mbox-cells = <2>;
851 gpi_dma2: dma-controller@800000 {
852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
853 #dma-cells = <3>;
867 dma-channels = <12>;
868 dma-channel-mask = <0x3e>;
870 dma-coherent;
875 compatible = "qcom,geni-se-qup";
878 clock-names = "m-ahb", "s-ahb";
879 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
880 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
882 dma-coherent;
883 #address-cells = <2>;
884 #size-cells = <2>;
888 compatible = "qcom,geni-i2c";
890 clock-names = "se";
891 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&qup_i2c8_data_clk>;
895 #address-cells = <1>;
896 #size-cells = <0>;
903 interconnect-names = "qup-core", "qup-config", "qup-memory";
906 dma-names = "tx", "rx";
907 power-domains = <&rpmhpd RPMHPD_CX>;
908 operating-points-v2 = <&qup_opp_table_120mhz>;
913 compatible = "qcom,geni-spi";
915 clock-names = "se";
916 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
918 pinctrl-names = "default";
919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
926 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 dma-names = "tx", "rx";
930 power-domains = <&rpmhpd RPMHPD_CX>;
931 operating-points-v2 = <&qup_opp_table_120mhz>;
932 #address-cells = <1>;
933 #size-cells = <0>;
938 compatible = "qcom,geni-i2c";
940 clock-names = "se";
941 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
942 pinctrl-names = "default";
943 pinctrl-0 = <&qup_i2c9_data_clk>;
945 #address-cells = <1>;
946 #size-cells = <0>;
953 interconnect-names = "qup-core", "qup-config", "qup-memory";
956 dma-names = "tx", "rx";
957 power-domains = <&rpmhpd RPMHPD_CX>;
958 operating-points-v2 = <&qup_opp_table_120mhz>;
963 compatible = "qcom,geni-spi";
965 clock-names = "se";
966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
976 interconnect-names = "qup-core", "qup-config", "qup-memory";
979 dma-names = "tx", "rx";
980 power-domains = <&rpmhpd RPMHPD_CX>;
981 operating-points-v2 = <&qup_opp_table_120mhz>;
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
991 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c10_data_clk>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1003 interconnect-names = "qup-core", "qup-config", "qup-memory";
1006 dma-names = "tx", "rx";
1007 power-domains = <&rpmhpd RPMHPD_CX>;
1008 operating-points-v2 = <&qup_opp_table_120mhz>;
1013 compatible = "qcom,geni-spi";
1015 clock-names = "se";
1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1026 interconnect-names = "qup-core", "qup-config", "qup-memory";
1029 dma-names = "tx", "rx";
1030 power-domains = <&rpmhpd RPMHPD_CX>;
1031 operating-points-v2 = <&qup_opp_table_120mhz>;
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1038 compatible = "qcom,geni-i2c";
1040 clock-names = "se";
1041 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&qup_i2c11_data_clk>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1056 dma-names = "tx", "rx";
1057 power-domains = <&rpmhpd RPMHPD_CX>;
1058 operating-points-v2 = <&qup_opp_table_120mhz>;
1063 compatible = "qcom,geni-spi";
1065 clock-names = "se";
1066 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1076 interconnect-names = "qup-core", "qup-config", "qup-memory";
1079 dma-names = "tx", "rx";
1080 power-domains = <&rpmhpd RPMHPD_CX>;
1081 operating-points-v2 = <&qup_opp_table_120mhz>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1088 compatible = "qcom,geni-i2c";
1090 clock-names = "se";
1091 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c12_data_clk>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1103 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 dma-names = "tx", "rx";
1107 power-domains = <&rpmhpd RPMHPD_CX>;
1108 operating-points-v2 = <&qup_opp_table_120mhz>;
1113 compatible = "qcom,geni-spi";
1115 clock-names = "se";
1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1126 interconnect-names = "qup-core", "qup-config", "qup-memory";
1129 dma-names = "tx", "rx";
1130 power-domains = <&rpmhpd RPMHPD_CX>;
1131 operating-points-v2 = <&qup_opp_table_120mhz>;
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1138 compatible = "qcom,geni-i2c";
1140 clock-names = "se";
1141 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&qup_i2c13_data_clk>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1153 interconnect-names = "qup-core", "qup-config", "qup-memory";
1156 dma-names = "tx", "rx";
1157 power-domains = <&rpmhpd RPMHPD_CX>;
1158 operating-points-v2 = <&qup_opp_table_120mhz>;
1163 compatible = "qcom,geni-spi";
1165 clock-names = "se";
1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1176 interconnect-names = "qup-core", "qup-config", "qup-memory";
1179 dma-names = "tx", "rx";
1180 power-domains = <&rpmhpd RPMHPD_CX>;
1181 operating-points-v2 = <&qup_opp_table_120mhz>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1188 compatible = "qcom,geni-uart";
1190 clock-names = "se";
1191 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1199 interconnect-names = "qup-core", "qup-config";
1200 power-domains = <&rpmhpd RPMHPD_CX>;
1201 operating-points-v2 = <&qup_opp_table_125mhz>;
1206 compatible = "qcom,geni-i2c";
1208 clock-names = "se";
1209 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&qup_i2c15_data_clk>;
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1221 interconnect-names = "qup-core", "qup-config", "qup-memory";
1224 dma-names = "tx", "rx";
1225 power-domains = <&rpmhpd RPMHPD_CX>;
1226 operating-points-v2 = <&qup_opp_table_100mhz>;
1231 compatible = "qcom,geni-spi";
1233 clock-names = "se";
1234 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1244 interconnect-names = "qup-core", "qup-config", "qup-memory";
1247 dma-names = "tx", "rx";
1248 power-domains = <&rpmhpd RPMHPD_CX>;
1249 operating-points-v2 = <&qup_opp_table_100mhz>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1257 compatible = "qcom,geni-se-i2c-master-hub";
1259 clock-names = "s-ahb";
1260 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1261 #address-cells = <2>;
1262 #size-cells = <2>;
1267 compatible = "qcom,geni-i2c-master-hub";
1269 clock-names = "se", "core";
1270 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&hub_i2c0_data_clk>;
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1281 interconnect-names = "qup-core", "qup-config";
1282 power-domains = <&rpmhpd RPMHPD_CX>;
1283 required-opps = <&rpmhpd_opp_low_svs>;
1288 compatible = "qcom,geni-i2c-master-hub";
1290 clock-names = "se", "core";
1291 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&hub_i2c1_data_clk>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 interconnect-names = "qup-core", "qup-config";
1303 power-domains = <&rpmhpd RPMHPD_CX>;
1304 required-opps = <&rpmhpd_opp_low_svs>;
1309 compatible = "qcom,geni-i2c-master-hub";
1311 clock-names = "se", "core";
1312 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1313 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&hub_i2c2_data_clk>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1323 interconnect-names = "qup-core", "qup-config";
1324 power-domains = <&rpmhpd RPMHPD_CX>;
1325 required-opps = <&rpmhpd_opp_low_svs>;
1330 compatible = "qcom,geni-i2c-master-hub";
1332 clock-names = "se", "core";
1333 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&hub_i2c3_data_clk>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1344 interconnect-names = "qup-core", "qup-config";
1345 power-domains = <&rpmhpd RPMHPD_CX>;
1346 required-opps = <&rpmhpd_opp_low_svs>;
1351 compatible = "qcom,geni-i2c-master-hub";
1353 clock-names = "se", "core";
1354 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1355 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1356 pinctrl-names = "default";
1357 pinctrl-0 = <&hub_i2c4_data_clk>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1365 interconnect-names = "qup-core", "qup-config";
1366 power-domains = <&rpmhpd RPMHPD_CX>;
1367 required-opps = <&rpmhpd_opp_low_svs>;
1372 compatible = "qcom,geni-i2c-master-hub";
1374 clock-names = "se", "core";
1375 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1376 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1377 pinctrl-names = "default";
1378 pinctrl-0 = <&hub_i2c5_data_clk>;
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 interconnect-names = "qup-core", "qup-config";
1387 power-domains = <&rpmhpd RPMHPD_CX>;
1388 required-opps = <&rpmhpd_opp_low_svs>;
1393 compatible = "qcom,geni-i2c-master-hub";
1395 clock-names = "se", "core";
1396 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1397 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1398 pinctrl-names = "default";
1399 pinctrl-0 = <&hub_i2c6_data_clk>;
1401 #address-cells = <1>;
1402 #size-cells = <0>;
1407 interconnect-names = "qup-core", "qup-config";
1408 power-domains = <&rpmhpd RPMHPD_CX>;
1409 required-opps = <&rpmhpd_opp_low_svs>;
1414 compatible = "qcom,geni-i2c-master-hub";
1416 clock-names = "se", "core";
1417 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1418 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&hub_i2c7_data_clk>;
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1428 interconnect-names = "qup-core", "qup-config";
1429 power-domains = <&rpmhpd RPMHPD_CX>;
1430 required-opps = <&rpmhpd_opp_low_svs>;
1435 compatible = "qcom,geni-i2c-master-hub";
1437 clock-names = "se", "core";
1438 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1439 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&hub_i2c8_data_clk>;
1443 #address-cells = <1>;
1444 #size-cells = <0>;
1449 interconnect-names = "qup-core", "qup-config";
1450 power-domains = <&rpmhpd RPMHPD_CX>;
1451 required-opps = <&rpmhpd_opp_low_svs>;
1456 compatible = "qcom,geni-i2c-master-hub";
1458 clock-names = "se", "core";
1459 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1460 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1461 pinctrl-names = "default";
1462 pinctrl-0 = <&hub_i2c9_data_clk>;
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1470 interconnect-names = "qup-core", "qup-config";
1471 power-domains = <&rpmhpd RPMHPD_CX>;
1472 required-opps = <&rpmhpd_opp_low_svs>;
1477 gpi_dma1: dma-controller@a00000 {
1478 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1479 #dma-cells = <3>;
1493 dma-channels = <12>;
1494 dma-channel-mask = <0x1e>;
1496 dma-coherent;
1501 compatible = "qcom,geni-se-qup";
1504 clock-names = "m-ahb", "s-ahb";
1505 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1506 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1510 interconnect-names = "qup-core";
1511 dma-coherent;
1512 #address-cells = <2>;
1513 #size-cells = <2>;
1517 compatible = "qcom,geni-i2c";
1519 clock-names = "se";
1520 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1521 pinctrl-names = "default";
1522 pinctrl-0 = <&qup_i2c0_data_clk>;
1524 #address-cells = <1>;
1525 #size-cells = <0>;
1532 interconnect-names = "qup-core", "qup-config", "qup-memory";
1535 dma-names = "tx", "rx";
1536 power-domains = <&rpmhpd RPMHPD_CX>;
1537 operating-points-v2 = <&qup_opp_table_120mhz>;
1542 compatible = "qcom,geni-spi";
1544 clock-names = "se";
1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1547 pinctrl-names = "default";
1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1555 interconnect-names = "qup-core", "qup-config", "qup-memory";
1558 dma-names = "tx", "rx";
1559 power-domains = <&rpmhpd RPMHPD_CX>;
1560 operating-points-v2 = <&qup_opp_table_120mhz>;
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1567 compatible = "qcom,geni-i2c";
1569 clock-names = "se";
1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1571 pinctrl-names = "default";
1572 pinctrl-0 = <&qup_i2c1_data_clk>;
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1582 interconnect-names = "qup-core", "qup-config", "qup-memory";
1585 dma-names = "tx", "rx";
1586 power-domains = <&rpmhpd RPMHPD_CX>;
1587 operating-points-v2 = <&qup_opp_table_120mhz>;
1592 compatible = "qcom,geni-spi";
1594 clock-names = "se";
1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1608 dma-names = "tx", "rx";
1609 power-domains = <&rpmhpd RPMHPD_CX>;
1610 operating-points-v2 = <&qup_opp_table_120mhz>;
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1617 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c2_data_clk>;
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1632 interconnect-names = "qup-core", "qup-config", "qup-memory";
1635 dma-names = "tx", "rx";
1636 power-domains = <&rpmhpd RPMHPD_CX>;
1637 operating-points-v2 = <&qup_opp_table_100mhz>;
1642 compatible = "qcom,geni-spi";
1644 clock-names = "se";
1645 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1647 pinctrl-names = "default";
1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1655 interconnect-names = "qup-core", "qup-config", "qup-memory";
1658 dma-names = "tx", "rx";
1659 power-domains = <&rpmhpd RPMHPD_CX>;
1660 operating-points-v2 = <&qup_opp_table_100mhz>;
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1667 compatible = "qcom,geni-i2c";
1669 clock-names = "se";
1670 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1671 pinctrl-names = "default";
1672 pinctrl-0 = <&qup_i2c3_data_clk>;
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1682 interconnect-names = "qup-core", "qup-config", "qup-memory";
1685 dma-names = "tx", "rx";
1686 power-domains = <&rpmhpd RPMHPD_CX>;
1687 operating-points-v2 = <&qup_opp_table_100mhz>;
1692 compatible = "qcom,geni-spi";
1694 clock-names = "se";
1695 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1697 pinctrl-names = "default";
1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1705 interconnect-names = "qup-core", "qup-config", "qup-memory";
1708 dma-names = "tx", "rx";
1709 power-domains = <&rpmhpd RPMHPD_CX>;
1710 operating-points-v2 = <&qup_opp_table_100mhz>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1717 compatible = "qcom,geni-i2c";
1719 clock-names = "se";
1720 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1721 pinctrl-names = "default";
1722 pinctrl-0 = <&qup_i2c4_data_clk>;
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1732 interconnect-names = "qup-core", "qup-config", "qup-memory";
1735 dma-names = "tx", "rx";
1736 power-domains = <&rpmhpd RPMHPD_CX>;
1737 operating-points-v2 = <&qup_opp_table_100mhz>;
1742 compatible = "qcom,geni-spi";
1744 clock-names = "se";
1745 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1755 interconnect-names = "qup-core", "qup-config", "qup-memory";
1758 dma-names = "tx", "rx";
1759 power-domains = <&rpmhpd RPMHPD_CX>;
1760 operating-points-v2 = <&qup_opp_table_100mhz>;
1761 #address-cells = <1>;
1762 #size-cells = <0>;
1767 compatible = "qcom,geni-i2c";
1769 clock-names = "se";
1770 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1771 pinctrl-names = "default";
1772 pinctrl-0 = <&qup_i2c5_data_clk>;
1780 interconnect-names = "qup-core", "qup-config", "qup-memory";
1783 dma-names = "tx", "rx";
1784 power-domains = <&rpmhpd RPMHPD_CX>;
1785 operating-points-v2 = <&qup_opp_table_100mhz>;
1786 #address-cells = <1>;
1787 #size-cells = <0>;
1792 compatible = "qcom,geni-spi";
1794 clock-names = "se";
1795 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1797 pinctrl-names = "default";
1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1805 interconnect-names = "qup-core", "qup-config", "qup-memory";
1808 dma-names = "tx", "rx";
1809 power-domains = <&rpmhpd RPMHPD_CX>;
1810 operating-points-v2 = <&qup_opp_table_100mhz>;
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1817 compatible = "qcom,geni-i2c";
1819 clock-names = "se";
1820 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1821 pinctrl-names = "default";
1822 pinctrl-0 = <&qup_i2c6_data_clk>;
1830 interconnect-names = "qup-core", "qup-config", "qup-memory";
1833 dma-names = "tx", "rx";
1834 power-domains = <&rpmhpd RPMHPD_CX>;
1835 operating-points-v2 = <&qup_opp_table_100mhz>;
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1842 compatible = "qcom,geni-spi";
1844 clock-names = "se";
1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1847 pinctrl-names = "default";
1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1855 interconnect-names = "qup-core", "qup-config", "qup-memory";
1858 dma-names = "tx", "rx";
1859 power-domains = <&rpmhpd RPMHPD_CX>;
1860 operating-points-v2 = <&qup_opp_table_100mhz>;
1861 #address-cells = <1>;
1862 #size-cells = <0>;
1867 compatible = "qcom,geni-debug-uart";
1869 clock-names = "se";
1870 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1871 pinctrl-names = "default";
1872 pinctrl-0 = <&qup_uart7_default>;
1874 interconnect-names = "qup-core", "qup-config";
1879 power-domains = <&rpmhpd RPMHPD_CX>;
1880 operating-points-v2 = <&qup_opp_table_100mhz>;
1886 compatible = "qcom,sm8550-cnoc-main";
1888 #interconnect-cells = <2>;
1889 qcom,bcm-voters = <&apps_bcm_voter>;
1893 compatible = "qcom,sm8550-config-noc";
1895 #interconnect-cells = <2>;
1896 qcom,bcm-voters = <&apps_bcm_voter>;
1900 compatible = "qcom,sm8550-system-noc";
1902 #interconnect-cells = <2>;
1903 qcom,bcm-voters = <&apps_bcm_voter>;
1907 compatible = "qcom,sm8550-pcie-anoc";
1909 #interconnect-cells = <2>;
1910 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1911 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1912 qcom,bcm-voters = <&apps_bcm_voter>;
1916 compatible = "qcom,sm8550-aggre1-noc";
1918 #interconnect-cells = <2>;
1919 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1920 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1921 qcom,bcm-voters = <&apps_bcm_voter>;
1925 compatible = "qcom,sm8550-aggre2-noc";
1927 #interconnect-cells = <2>;
1929 qcom,bcm-voters = <&apps_bcm_voter>;
1933 compatible = "qcom,sm8550-mmss-noc";
1935 #interconnect-cells = <2>;
1936 qcom,bcm-voters = <&apps_bcm_voter>;
1940 compatible = "qcom,sm8550-trng", "qcom,trng";
1946 compatible = "qcom,pcie-sm8550";
1952 reg-names = "parf", "dbi", "elbi", "atu", "config";
1953 #address-cells = <3>;
1954 #size-cells = <2>;
1957 bus-range = <0x00 0xff>;
1959 dma-coherent;
1961 linux,pci-domain = <0>;
1962 num-lanes = <2>;
1973 interrupt-names = "msi0",
1982 #interrupt-cells = <1>;
1983 interrupt-map-mask = <0 0 0 0x7>;
1984 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */
1989 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1990 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1991 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1992 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1993 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1995 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1996 clock-names = "aux",
2008 interconnect-names = "pcie-mem", "cpu-pcie";
2010 msi-map = <0x0 &gic_its 0x1400 0x1>,
2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
2015 resets = <&gcc GCC_PCIE_0_BCR>;
2016 reset-names = "pci";
2018 power-domains = <&gcc PCIE_0_GDSC>;
2021 phy-names = "pciephy";
2023 operating-points-v2 = <&pcie0_opp_table>;
2027 pcie0_opp_table: opp-table {
2028 compatible = "operating-points-v2";
2031 opp-2500000-1 {
2032 opp-hz = /bits/ 64 <2500000>;
2033 required-opps = <&rpmhpd_opp_low_svs>;
2034 opp-peak-kBps = <250000 1>;
2035 opp-level = <1>;
2039 opp-5000000-1 {
2040 opp-hz = /bits/ 64 <5000000>;
2041 required-opps = <&rpmhpd_opp_low_svs>;
2042 opp-peak-kBps = <500000 1>;
2043 opp-level = <1>;
2047 opp-5000000-2 {
2048 opp-hz = /bits/ 64 <5000000>;
2049 required-opps = <&rpmhpd_opp_low_svs>;
2050 opp-peak-kBps = <500000 1>;
2051 opp-level = <2>;
2055 opp-10000000-2 {
2056 opp-hz = /bits/ 64 <10000000>;
2057 required-opps = <&rpmhpd_opp_low_svs>;
2058 opp-peak-kBps = <1000000 1>;
2059 opp-level = <2>;
2063 opp-8000000-3 {
2064 opp-hz = /bits/ 64 <8000000>;
2065 required-opps = <&rpmhpd_opp_nom>;
2066 opp-peak-kBps = <984500 1>;
2067 opp-level = <3>;
2071 opp-16000000-3 {
2072 opp-hz = /bits/ 64 <16000000>;
2073 required-opps = <&rpmhpd_opp_nom>;
2074 opp-peak-kBps = <1969000 1>;
2075 opp-level = <3>;
2082 bus-range = <0x01 0xff>;
2084 #address-cells = <3>;
2085 #size-cells = <2>;
2091 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
2094 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2095 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2097 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
2098 <&gcc GCC_PCIE_0_PIPE_CLK>;
2099 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2102 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2103 reset-names = "phy";
2105 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2106 assigned-clock-rates = <100000000>;
2108 power-domains = <&gcc PCIE_0_PHY_GDSC>;
2110 #clock-cells = <0>;
2111 clock-output-names = "pcie0_pipe_clk";
2113 #phy-cells = <0>;
2120 compatible = "qcom,pcie-sm8550";
2126 reg-names = "parf", "dbi", "elbi", "atu", "config";
2127 #address-cells = <3>;
2128 #size-cells = <2>;
2131 bus-range = <0x00 0xff>;
2133 dma-coherent;
2135 linux,pci-domain = <1>;
2136 num-lanes = <2>;
2147 interrupt-names = "msi0",
2156 #interrupt-cells = <1>;
2157 interrupt-map-mask = <0 0 0 0x7>;
2158 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */
2163 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2164 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2165 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2166 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2167 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2168 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
2169 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
2170 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
2171 clock-names = "aux",
2180 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2181 assigned-clock-rates = <19200000>;
2187 interconnect-names = "pcie-mem", "cpu-pcie";
2189 msi-map = <0x0 &gic_its 0x1480 0x1>,
2191 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
2194 resets = <&gcc GCC_PCIE_1_BCR>,
2195 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
2196 reset-names = "pci", "link_down";
2198 power-domains = <&gcc PCIE_1_GDSC>;
2201 phy-names = "pciephy";
2203 operating-points-v2 = <&pcie1_opp_table>;
2207 pcie1_opp_table: opp-table {
2208 compatible = "operating-points-v2";
2211 opp-2500000-1 {
2212 opp-hz = /bits/ 64 <2500000>;
2213 required-opps = <&rpmhpd_opp_low_svs>;
2214 opp-peak-kBps = <250000 1>;
2215 opp-level = <1>;
2219 opp-5000000-1 {
2220 opp-hz = /bits/ 64 <5000000>;
2221 required-opps = <&rpmhpd_opp_low_svs>;
2222 opp-peak-kBps = <500000 1>;
2223 opp-level = <1>;
2227 opp-5000000-2 {
2228 opp-hz = /bits/ 64 <5000000>;
2229 required-opps = <&rpmhpd_opp_low_svs>;
2230 opp-peak-kBps = <500000 1>;
2231 opp-level = <2>;
2235 opp-10000000-2 {
2236 opp-hz = /bits/ 64 <10000000>;
2237 required-opps = <&rpmhpd_opp_low_svs>;
2238 opp-peak-kBps = <1000000 1>;
2239 opp-level = <2>;
2243 opp-8000000-3 {
2244 opp-hz = /bits/ 64 <8000000>;
2245 required-opps = <&rpmhpd_opp_nom>;
2246 opp-peak-kBps = <984500 1>;
2247 opp-level = <3>;
2251 opp-16000000-3 {
2252 opp-hz = /bits/ 64 <16000000>;
2253 required-opps = <&rpmhpd_opp_nom>;
2254 opp-peak-kBps = <1969000 1>;
2255 opp-level = <3>;
2259 opp-16000000-4 {
2260 opp-hz = /bits/ 64 <16000000>;
2261 required-opps = <&rpmhpd_opp_nom>;
2262 opp-peak-kBps = <1969000 1>;
2263 opp-level = <4>;
2267 opp-32000000-4 {
2268 opp-hz = /bits/ 64 <32000000>;
2269 required-opps = <&rpmhpd_opp_nom>;
2270 opp-peak-kBps = <3938000 1>;
2271 opp-level = <4>;
2278 bus-range = <0x01 0xff>;
2280 #address-cells = <3>;
2281 #size-cells = <2>;
2287 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
2290 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2291 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2293 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2294 <&gcc GCC_PCIE_1_PIPE_CLK>;
2295 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2298 resets = <&gcc GCC_PCIE_1_PHY_BCR>,
2299 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
2300 reset-names = "phy", "phy_nocsr";
2302 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2303 assigned-clock-rates = <100000000>;
2305 power-domains = <&gcc PCIE_1_PHY_GDSC>;
2307 #clock-cells = <1>;
2308 clock-output-names = "pcie1_pipe_clk";
2310 #phy-cells = <0>;
2315 cryptobam: dma-controller@1dc4000 {
2316 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2319 #dma-cells = <1>;
2321 qcom,num-ees = <4>;
2322 num-channels = <20>;
2323 qcom,controlled-remotely;
2329 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
2332 dma-names = "rx", "tx";
2337 interconnect-names = "memory";
2341 compatible = "qcom,sm8550-qmp-ufs-phy";
2344 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2346 clock-names = "ref",
2350 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
2353 reset-names = "ufsphy";
2355 #clock-cells = <1>;
2356 #phy-cells = <0>;
2362 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
2363 "jedec,ufs-2.0";
2367 phy-names = "ufsphy";
2368 lanes-per-direction = <2>;
2369 #reset-cells = <1>;
2370 resets = <&gcc GCC_UFS_PHY_BCR>;
2371 reset-names = "rst";
2373 power-domains = <&gcc UFS_PHY_GDSC>;
2374 required-opps = <&rpmhpd_opp_nom>;
2377 dma-coherent;
2379 operating-points-v2 = <&ufs_opp_table>;
2385 interconnect-names = "ufs-ddr", "cpu-ufs";
2386 clock-names = "core_clk",
2394 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2395 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2396 <&gcc GCC_UFS_PHY_AHB_CLK>,
2397 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2399 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2400 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2401 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2406 ufs_opp_table: opp-table {
2407 compatible = "operating-points-v2";
2409 opp-75000000 {
2410 opp-hz = /bits/ 64 <75000000>,
2418 required-opps = <&rpmhpd_opp_low_svs>;
2421 opp-150000000 {
2422 opp-hz = /bits/ 64 <150000000>,
2430 required-opps = <&rpmhpd_opp_svs>;
2433 opp-300000000 {
2434 opp-hz = /bits/ 64 <300000000>,
2442 required-opps = <&rpmhpd_opp_nom>;
2448 compatible = "qcom,sm8550-inline-crypto-engine",
2449 "qcom,inline-crypto-engine";
2452 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2456 compatible = "qcom,tcsr-mutex";
2458 #hwlock-cells = <1>;
2461 tcsr: clock-controller@1fc0000 {
2462 compatible = "qcom,sm8550-tcsr", "syscon";
2465 #clock-cells = <1>;
2466 #reset-cells = <1>;
2470 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2474 reg-names = "kgsl_3d0_reg_memory",
2483 operating-points-v2 = <&gpu_opp_table>;
2486 #cooling-cells = <2>;
2490 interconnect-names = "gfx-mem";
2494 gpu_zap_shader: zap-shader {
2495 memory-region = <&gpu_micro_code_mem>;
2499 gpu_opp_table: opp-table {
2500 compatible = "operating-points-v2";
2502 opp-680000000 {
2503 opp-hz = /bits/ 64 <680000000>;
2504 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2505 opp-peak-kBps = <16500000>;
2508 opp-615000000 {
2509 opp-hz = /bits/ 64 <615000000>;
2510 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2511 opp-peak-kBps = <12449218>;
2514 opp-550000000 {
2515 opp-hz = /bits/ 64 <550000000>;
2516 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2517 opp-peak-kBps = <10687500>;
2520 opp-475000000 {
2521 opp-hz = /bits/ 64 <475000000>;
2522 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2523 opp-peak-kBps = <6074218>;
2526 opp-401000000 {
2527 opp-hz = /bits/ 64 <401000000>;
2528 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2529 opp-peak-kBps = <6074218>;
2532 opp-348000000 {
2533 opp-hz = /bits/ 64 <348000000>;
2534 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2535 opp-peak-kBps = <6074218>;
2538 opp-295000000 {
2539 opp-hz = /bits/ 64 <295000000>;
2540 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2541 opp-peak-kBps = <6074218>;
2544 opp-220000000 {
2545 opp-hz = /bits/ 64 <220000000>;
2546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2547 opp-peak-kBps = <2136718>;
2553 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2557 reg-names = "gmu", "rscc", "gmu_pdc";
2561 interrupt-names = "hfi", "gmu";
2566 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2567 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2570 clock-names = "ahb",
2578 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2580 power-domain-names = "cx",
2587 operating-points-v2 = <&gmu_opp_table>;
2589 gmu_opp_table: opp-table {
2590 compatible = "operating-points-v2";
2592 opp-500000000 {
2593 opp-hz = /bits/ 64 <500000000>;
2594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2597 opp-200000000 {
2598 opp-hz = /bits/ 64 <200000000>;
2599 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2604 gpucc: clock-controller@3d90000 {
2605 compatible = "qcom,sm8550-gpucc";
2608 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2609 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2610 #clock-cells = <1>;
2611 #reset-cells = <1>;
2612 #power-domain-cells = <1>;
2616 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2617 "qcom,smmu-500", "arm,mmu-500";
2619 #iommu-cells = <2>;
2620 #global-interrupts = <1>;
2648 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2649 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2651 clock-names = "hlos",
2655 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2656 dma-coherent;
2660 compatible = "qcom,sm8550-ipa";
2667 reg-names = "ipa-reg",
2668 "ipa-shared",
2671 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>,
2675 interrupt-names = "ipa",
2677 "ipa-clock-query",
2678 "ipa-setup-ready";
2681 clock-names = "core";
2687 interconnect-names = "memory",
2692 qcom,smem-states = <&ipa_smp2p_out 0>,
2694 qcom,smem-state-names = "ipa-clock-enabled-valid",
2695 "ipa-clock-enabled";
2701 compatible = "qcom,sm8550-mpss-pas";
2704 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
2710 interrupt-names = "wdog", "fatal", "ready", "handover",
2711 "stop-ack", "shutdown-ack";
2714 clock-names = "xo";
2716 power-domains = <&rpmhpd RPMHPD_CX>,
2718 power-domain-names = "cx", "mss";
2723 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2727 qcom,smem-states = <&smp2p_modem_out 0>;
2728 qcom,smem-state-names = "stop";
2732 glink-edge {
2733 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2739 qcom,remote-pid = <1>;
2744 compatible = "qcom,sm8550-adsp-pas";
2747 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2752 interrupt-names = "wdog", "fatal", "ready",
2753 "handover", "stop-ack";
2756 clock-names = "xo";
2758 power-domains = <&rpmhpd RPMHPD_LCX>,
2760 power-domain-names = "lcx", "lmx";
2765 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
2769 qcom,smem-states = <&smp2p_adsp_out 0>;
2770 qcom,smem-state-names = "stop";
2774 remoteproc_adsp_glink: glink-edge {
2775 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2782 qcom,remote-pid = <2>;
2786 qcom,glink-channels = "fastrpcglink-apps-dsp";
2788 qcom,non-secure-domain;
2789 #address-cells = <1>;
2790 #size-cells = <0>;
2792 compute-cb@3 {
2793 compatible = "qcom,fastrpc-compute-cb";
2797 dma-coherent;
2800 compute-cb@4 {
2801 compatible = "qcom,fastrpc-compute-cb";
2805 dma-coherent;
2808 compute-cb@5 {
2809 compatible = "qcom,fastrpc-compute-cb";
2813 dma-coherent;
2816 compute-cb@6 {
2817 compatible = "qcom,fastrpc-compute-cb";
2821 dma-coherent;
2824 compute-cb@7 {
2825 compatible = "qcom,fastrpc-compute-cb";
2829 dma-coherent;
2835 qcom,glink-channels = "adsp_apps";
2838 #address-cells = <1>;
2839 #size-cells = <0>;
2844 #sound-dai-cells = <0>;
2845 qcom,protection-domain = "avs/audio",
2849 compatible = "qcom,q6apm-dais";
2855 compatible = "qcom,q6apm-lpass-dais";
2856 #sound-dai-cells = <1>;
2863 qcom,protection-domain = "avs/audio",
2866 q6prmcc: clock-controller {
2867 compatible = "qcom,q6prm-lpass-clocks";
2868 #clock-cells = <2>;
2876 compatible = "qcom,sm8550-lpass-wsa-macro";
2882 clock-names = "mclk", "macro", "dcodec", "fsgen";
2884 #clock-cells = <0>;
2885 clock-output-names = "wsa2-mclk";
2886 #sound-dai-cells = <1>;
2890 compatible = "qcom,soundwire-v2.0.0";
2894 clock-names = "iface";
2897 pinctrl-0 = <&wsa2_swr_active>;
2898 pinctrl-names = "default";
2900 qcom,din-ports = <4>;
2901 qcom,dout-ports = <9>;
2903 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2904 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2905 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2906 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2907 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2908 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2909 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2910 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2911 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2913 #address-cells = <2>;
2914 #size-cells = <0>;
2915 #sound-dai-cells = <1>;
2920 compatible = "qcom,sm8550-lpass-rx-macro";
2926 clock-names = "mclk", "macro", "dcodec", "fsgen";
2928 #clock-cells = <0>;
2929 clock-output-names = "mclk";
2930 #sound-dai-cells = <1>;
2934 compatible = "qcom,soundwire-v2.0.0";
2938 clock-names = "iface";
2941 pinctrl-0 = <&rx_swr_active>;
2942 pinctrl-names = "default";
2944 qcom,din-ports = <1>;
2945 qcom,dout-ports = <11>;
2947 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2948 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2949 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2950 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2951 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2952 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2953 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff…
2954 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0x…
2955 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2957 #address-cells = <2>;
2958 #size-cells = <0>;
2959 #sound-dai-cells = <1>;
2964 compatible = "qcom,sm8550-lpass-tx-macro";
2970 clock-names = "mclk", "macro", "dcodec", "fsgen";
2972 #clock-cells = <0>;
2973 clock-output-names = "mclk";
2974 #sound-dai-cells = <1>;
2978 compatible = "qcom,sm8550-lpass-wsa-macro";
2984 clock-names = "mclk", "macro", "dcodec", "fsgen";
2986 #clock-cells = <0>;
2987 clock-output-names = "mclk";
2988 #sound-dai-cells = <1>;
2992 compatible = "qcom,soundwire-v2.0.0";
2996 clock-names = "iface";
2999 pinctrl-0 = <&wsa_swr_active>;
3000 pinctrl-names = "default";
3002 qcom,din-ports = <4>;
3003 qcom,dout-ports = <9>;
3005 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
3006 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3007 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3008 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3009 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3010 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3011 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3012 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3013 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3015 #address-cells = <2>;
3016 #size-cells = <0>;
3017 #sound-dai-cells = <1>;
3022 compatible = "qcom,soundwire-v2.0.0";
3026 interrupt-names = "core", "wakeup";
3028 clock-names = "iface";
3031 pinctrl-0 = <&tx_swr_active>;
3032 pinctrl-names = "default";
3034 qcom,din-ports = <4>;
3035 qcom,dout-ports = <0>;
3036 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3037 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3038 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3039 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3040 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3041 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3042 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3043 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3044 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3046 #address-cells = <2>;
3047 #size-cells = <0>;
3048 #sound-dai-cells = <1>;
3053 compatible = "qcom,sm8550-lpass-va-macro";
3058 clock-names = "mclk", "macro", "dcodec";
3060 #clock-cells = <0>;
3061 clock-output-names = "fsgen";
3062 #sound-dai-cells = <1>;
3066 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
3069 gpio-controller;
3070 #gpio-cells = <2>;
3071 gpio-ranges = <&lpass_tlmm 0 0 23>;
3075 clock-names = "core", "audio";
3077 tx_swr_active: tx-swr-active-state {
3078 clk-pins {
3081 drive-strength = <2>;
3082 slew-rate = <1>;
3083 bias-disable;
3086 data-pins {
3089 drive-strength = <2>;
3090 slew-rate = <1>;
3091 bias-bus-hold;
3095 rx_swr_active: rx-swr-active-state {
3096 clk-pins {
3099 drive-strength = <2>;
3100 slew-rate = <1>;
3101 bias-disable;
3104 data-pins {
3107 drive-strength = <2>;
3108 slew-rate = <1>;
3109 bias-bus-hold;
3113 dmic01_default: dmic01-default-state {
3114 clk-pins {
3117 drive-strength = <8>;
3118 output-high;
3121 data-pins {
3124 drive-strength = <8>;
3125 input-enable;
3129 dmic23_default: dmic23-default-state {
3130 clk-pins {
3133 drive-strength = <8>;
3134 output-high;
3137 data-pins {
3140 drive-strength = <8>;
3141 input-enable;
3145 wsa_swr_active: wsa-swr-active-state {
3146 clk-pins {
3149 drive-strength = <2>;
3150 slew-rate = <1>;
3151 bias-disable;
3154 data-pins {
3157 drive-strength = <2>;
3158 slew-rate = <1>;
3159 bias-bus-hold;
3163 wsa2_swr_active: wsa2-swr-active-state {
3164 clk-pins {
3167 drive-strength = <2>;
3168 slew-rate = <1>;
3169 bias-disable;
3172 data-pins {
3175 drive-strength = <2>;
3176 slew-rate = <1>;
3177 bias-bus-hold;
3183 compatible = "qcom,sm8550-lpass-lpiaon-noc";
3185 #interconnect-cells = <2>;
3186 qcom,bcm-voters = <&apps_bcm_voter>;
3190 compatible = "qcom,sm8550-lpass-lpicx-noc";
3192 #interconnect-cells = <2>;
3193 qcom,bcm-voters = <&apps_bcm_voter>;
3197 compatible = "qcom,sm8550-lpass-ag-noc";
3199 #interconnect-cells = <2>;
3200 qcom,bcm-voters = <&apps_bcm_voter>;
3204 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
3209 interrupt-names = "hc_irq", "pwr_irq";
3211 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3212 <&gcc GCC_SDCC2_APPS_CLK>,
3214 clock-names = "iface", "core", "xo";
3216 qcom,dll-config = <0x0007642c>;
3217 qcom,ddr-config = <0x80040868>;
3218 power-domains = <&rpmhpd RPMHPD_CX>;
3219 operating-points-v2 = <&sdhc2_opp_table>;
3225 interconnect-names = "sdhc-ddr", "cpu-sdhc";
3226 bus-width = <4>;
3227 max-sd-hs-hz = <37500000>;
3228 dma-coherent;
3230 /* Forbid SDR104/SDR50 - broken hw! */
3231 sdhci-caps-mask = <0x3 0>;
3235 sdhc2_opp_table: opp-table {
3236 compatible = "operating-points-v2";
3238 opp-19200000 {
3239 opp-hz = /bits/ 64 <19200000>;
3240 required-opps = <&rpmhpd_opp_min_svs>;
3243 opp-50000000 {
3244 opp-hz = /bits/ 64 <50000000>;
3245 required-opps = <&rpmhpd_opp_low_svs>;
3248 opp-100000000 {
3249 opp-hz = /bits/ 64 <100000000>;
3250 required-opps = <&rpmhpd_opp_svs>;
3253 opp-202000000 {
3254 opp-hz = /bits/ 64 <202000000>;
3255 required-opps = <&rpmhpd_opp_svs_l1>;
3260 iris: video-codec@aa00000 {
3261 compatible = "qcom,sm8550-iris";
3266 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
3270 power-domain-names = "venus",
3274 operating-points-v2 = <&iris_opp_table>;
3276 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3279 clock-names = "iface",
3287 interconnect-names = "cpu-cfg",
3288 "video-mem";
3290 memory-region = <&video_mem>;
3292 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
3293 reset-names = "bus";
3297 dma-coherent;
3306 iris_opp_table: opp-table {
3307 compatible = "operating-points-v2";
3309 opp-240000000 {
3310 opp-hz = /bits/ 64 <240000000>;
3311 required-opps = <&rpmhpd_opp_svs>,
3315 opp-338000000 {
3316 opp-hz = /bits/ 64 <338000000>;
3317 required-opps = <&rpmhpd_opp_svs>,
3321 opp-366000000 {
3322 opp-hz = /bits/ 64 <366000000>;
3323 required-opps = <&rpmhpd_opp_svs_l1>,
3327 opp-444000000 {
3328 opp-hz = /bits/ 64 <444000000>;
3329 required-opps = <&rpmhpd_opp_nom>,
3333 opp-533333334 {
3334 opp-hz = /bits/ 64 <533333334>;
3335 required-opps = <&rpmhpd_opp_turbo>,
3341 videocc: clock-controller@aaf0000 {
3342 compatible = "qcom,sm8550-videocc";
3345 <&gcc GCC_VIDEO_AHB_CLK>;
3346 power-domains = <&rpmhpd RPMHPD_MMCX>,
3348 required-opps = <&rpmhpd_opp_low_svs>,
3350 #clock-cells = <1>;
3351 #reset-cells = <1>;
3352 #power-domain-cells = <1>;
3356 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
3359 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3363 clock-names = "camnoc_axi",
3366 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3367 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3368 pinctrl-names = "default", "sleep";
3370 #address-cells = <1>;
3371 #size-cells = <0>;
3373 cci0_i2c0: i2c-bus@0 {
3375 clock-frequency = <1000000>;
3376 #address-cells = <1>;
3377 #size-cells = <0>;
3380 cci0_i2c1: i2c-bus@1 {
3382 clock-frequency = <1000000>;
3383 #address-cells = <1>;
3384 #size-cells = <0>;
3389 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
3392 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3396 clock-names = "camnoc_axi",
3399 pinctrl-0 = <&cci1_0_default>;
3400 pinctrl-1 = <&cci1_0_sleep>;
3401 pinctrl-names = "default", "sleep";
3403 #address-cells = <1>;
3404 #size-cells = <0>;
3406 cci1_i2c0: i2c-bus@0 {
3408 clock-frequency = <1000000>;
3409 #address-cells = <1>;
3410 #size-cells = <0>;
3415 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci";
3418 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
3422 clock-names = "camnoc_axi",
3425 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3426 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3427 pinctrl-names = "default", "sleep";
3429 #address-cells = <1>;
3430 #size-cells = <0>;
3432 cci2_i2c0: i2c-bus@0 {
3434 clock-frequency = <1000000>;
3435 #address-cells = <1>;
3436 #size-cells = <0>;
3439 cci2_i2c1: i2c-bus@1 {
3441 clock-frequency = <1000000>;
3442 #address-cells = <1>;
3443 #size-cells = <0>;
3448 compatible = "qcom,sm8550-camss";
3469 reg-names = "csid0",
3514 <&gcc GCC_CAMERA_HF_AXI_CLK>,
3525 clock-names = "camnoc_axi",
3580 interrupt-names = "csid0",
3603 interconnect-names = "ahb",
3608 power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
3612 power-domain-names = "ife0",
3620 #address-cells = <1>;
3621 #size-cells = <0>;
3657 camcc: clock-controller@ade0000 {
3658 compatible = "qcom,sm8550-camcc";
3660 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3664 power-domains = <&rpmhpd RPMHPD_MMCX>,
3666 required-opps = <&rpmhpd_opp_low_svs>,
3668 #clock-cells = <1>;
3669 #reset-cells = <1>;
3670 #power-domain-cells = <1>;
3673 mdss: display-subsystem@ae00000 {
3674 compatible = "qcom,sm8550-mdss";
3676 reg-names = "mdss";
3679 interrupt-controller;
3680 #interrupt-cells = <1>;
3683 <&gcc GCC_DISP_AHB_CLK>,
3684 <&gcc GCC_DISP_HF_AXI_CLK>,
3689 power-domains = <&dispcc MDSS_GDSC>;
3695 interconnect-names = "mdp0-mem", "cpu-cfg";
3699 #address-cells = <2>;
3700 #size-cells = <2>;
3705 mdss_mdp: display-controller@ae01000 {
3706 compatible = "qcom,sm8550-dpu";
3709 reg-names = "mdp", "vbif";
3711 interrupt-parent = <&mdss>;
3714 clocks = <&gcc GCC_DISP_AHB_CLK>,
3715 <&gcc GCC_DISP_HF_AXI_CLK>,
3720 clock-names = "bus",
3727 power-domains = <&rpmhpd RPMHPD_MMCX>;
3729 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3730 assigned-clock-rates = <19200000>;
3732 operating-points-v2 = <&mdp_opp_table>;
3735 #address-cells = <1>;
3736 #size-cells = <0>;
3741 remote-endpoint = <&mdss_dsi0_in>;
3748 remote-endpoint = <&mdss_dsi1_in>;
3755 remote-endpoint = <&mdss_dp0_in>;
3760 mdp_opp_table: opp-table {
3761 compatible = "operating-points-v2";
3763 opp-200000000 {
3764 opp-hz = /bits/ 64 <200000000>;
3765 required-opps = <&rpmhpd_opp_low_svs>;
3768 opp-325000000 {
3769 opp-hz = /bits/ 64 <325000000>;
3770 required-opps = <&rpmhpd_opp_svs>;
3773 opp-375000000 {
3774 opp-hz = /bits/ 64 <375000000>;
3775 required-opps = <&rpmhpd_opp_svs_l1>;
3778 opp-514000000 {
3779 opp-hz = /bits/ 64 <514000000>;
3780 required-opps = <&rpmhpd_opp_nom>;
3785 mdss_dp0: displayport-controller@ae90000 {
3786 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
3792 interrupt-parent = <&mdss>;
3800 clock-names = "core_iface",
3807 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3810 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3815 phy-names = "dp";
3817 #sound-dai-cells = <0>;
3819 operating-points-v2 = <&dp_opp_table>;
3820 power-domains = <&rpmhpd RPMHPD_MMCX>;
3825 #address-cells = <1>;
3826 #size-cells = <0>;
3831 remote-endpoint = <&dpu_intf0_out>;
3838 data-lanes = <0 1 2 3>;
3839 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
3844 dp_opp_table: opp-table {
3845 compatible = "operating-points-v2";
3847 opp-162000000 {
3848 opp-hz = /bits/ 64 <162000000>;
3849 required-opps = <&rpmhpd_opp_low_svs_d1>;
3852 opp-270000000 {
3853 opp-hz = /bits/ 64 <270000000>;
3854 required-opps = <&rpmhpd_opp_low_svs>;
3857 opp-540000000 {
3858 opp-hz = /bits/ 64 <540000000>;
3859 required-opps = <&rpmhpd_opp_svs_l1>;
3862 opp-810000000 {
3863 opp-hz = /bits/ 64 <810000000>;
3864 required-opps = <&rpmhpd_opp_nom>;
3870 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3872 reg-names = "dsi_ctrl";
3874 interrupt-parent = <&mdss>;
3882 <&gcc GCC_DISP_HF_AXI_CLK>;
3883 clock-names = "byte",
3890 power-domains = <&rpmhpd RPMHPD_MMCX>;
3892 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3894 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
3897 operating-points-v2 = <&mdss_dsi_opp_table>;
3900 phy-names = "dsi";
3902 #address-cells = <1>;
3903 #size-cells = <0>;
3908 #address-cells = <1>;
3909 #size-cells = <0>;
3914 remote-endpoint = <&dpu_intf1_out>;
3925 mdss_dsi_opp_table: opp-table {
3926 compatible = "operating-points-v2";
3928 opp-187500000 {
3929 opp-hz = /bits/ 64 <187500000>;
3930 required-opps = <&rpmhpd_opp_low_svs>;
3933 opp-300000000 {
3934 opp-hz = /bits/ 64 <300000000>;
3935 required-opps = <&rpmhpd_opp_svs>;
3938 opp-358000000 {
3939 opp-hz = /bits/ 64 <358000000>;
3940 required-opps = <&rpmhpd_opp_svs_l1>;
3946 compatible = "qcom,sm8550-dsi-phy-4nm";
3950 reg-names = "dsi_phy",
3956 clock-names = "iface", "ref";
3958 #clock-cells = <1>;
3959 #phy-cells = <0>;
3965 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3967 reg-names = "dsi_ctrl";
3969 interrupt-parent = <&mdss>;
3977 <&gcc GCC_DISP_HF_AXI_CLK>;
3978 clock-names = "byte",
3985 power-domains = <&rpmhpd RPMHPD_MMCX>;
3987 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3989 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
3992 operating-points-v2 = <&mdss_dsi_opp_table>;
3995 phy-names = "dsi";
3997 #address-cells = <1>;
3998 #size-cells = <0>;
4003 #address-cells = <1>;
4004 #size-cells = <0>;
4009 remote-endpoint = <&dpu_intf2_out>;
4022 compatible = "qcom,sm8550-dsi-phy-4nm";
4026 reg-names = "dsi_phy",
4032 clock-names = "iface", "ref";
4034 #clock-cells = <1>;
4035 #phy-cells = <0>;
4041 dispcc: clock-controller@af00000 {
4042 compatible = "qcom,sm8550-dispcc";
4046 <&gcc GCC_DISP_AHB_CLK>,
4060 power-domains = <&rpmhpd RPMHPD_MMCX>;
4061 required-opps = <&rpmhpd_opp_low_svs>;
4062 #clock-cells = <1>;
4063 #reset-cells = <1>;
4064 #power-domain-cells = <1>;
4068 compatible = "qcom,sm8550-snps-eusb2-phy";
4070 #phy-cells = <0>;
4073 clock-names = "ref";
4075 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
4081 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
4084 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
4086 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
4087 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4088 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
4090 power-domains = <&gcc USB3_PHY_GDSC>;
4092 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4093 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4094 reset-names = "phy", "common";
4096 #clock-cells = <1>;
4097 #phy-cells = <1>;
4099 mode-switch;
4100 orientation-switch;
4105 #address-cells = <1>;
4106 #size-cells = <0>;
4119 remote-endpoint = <&usb_1_dwc3_ss>;
4127 remote-endpoint = <&mdss_dp0_out>;
4134 compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3";
4136 #address-cells = <1>;
4137 #size-cells = <0>;
4139 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4140 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4141 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4142 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4143 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4145 clock-names = "cfg_noc",
4152 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4153 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4154 assigned-clock-rates = <19200000>, <200000000>;
4156 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
4162 interrupt-names = "dwc_usb3",
4169 power-domains = <&gcc USB30_PRIM_GDSC>;
4170 required-opps = <&rpmhpd_opp_nom>;
4172 resets = <&gcc GCC_USB30_PRIM_BCR>;
4178 interconnect-names = "usb-ddr", "apps-usb";
4184 phy-names = "usb2-phy", "usb3-phy";
4186 snps,hird-threshold = /bits/ 8 <0x0>;
4187 snps,usb2-gadget-lpm-disable;
4190 snps,dis-u1-entry-quirk;
4191 snps,dis-u2-entry-quirk;
4192 snps,is-utmi-l1-suspend;
4194 snps,usb2-lpm-disable;
4195 snps,has-lpm-erratum;
4196 tx-fifo-resize;
4198 dma-coherent;
4200 usb-role-switch;
4205 #address-cells = <1>;
4206 #size-cells = <0>;
4219 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4225 pdc: interrupt-controller@b220000 {
4226 compatible = "qcom,sm8550-pdc", "qcom,pdc";
4228 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4231 #interrupt-cells = <2>;
4232 interrupt-parent = <&intc>;
4233 interrupt-controller;
4236 tsens0: thermal-sensor@c271000 {
4237 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
4243 interrupt-names = "uplow", "critical";
4244 #thermal-sensor-cells = <1>;
4247 tsens1: thermal-sensor@c272000 {
4248 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
4254 interrupt-names = "uplow", "critical";
4255 #thermal-sensor-cells = <1>;
4258 tsens2: thermal-sensor@c273000 {
4259 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
4265 interrupt-names = "uplow", "critical";
4266 #thermal-sensor-cells = <1>;
4269 aoss_qmp: power-management@c300000 {
4270 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
4272 interrupt-parent = <&ipcc>;
4273 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4277 #clock-cells = <0>;
4281 compatible = "qcom,rpmh-stats";
4287 compatible = "qcom,spmi-pmic-arb";
4293 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4294 interrupt-names = "periph_irq";
4295 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4298 qcom,bus-id = <0>;
4299 #address-cells = <2>;
4300 #size-cells = <0>;
4301 interrupt-controller;
4302 #interrupt-cells = <4>;
4306 compatible = "qcom,sm8550-tlmm";
4309 gpio-controller;
4310 #gpio-cells = <2>;
4311 interrupt-controller;
4312 #interrupt-cells = <2>;
4313 gpio-ranges = <&tlmm 0 0 211>;
4314 wakeup-parent = <&pdc>;
4316 cam0_default: cam0-default-state {
4317 mclk-pins {
4320 drive-strength = <2>;
4321 bias-disable;
4325 cam0_sleep: cam0-sleep-state {
4326 mclk-pins {
4329 drive-strength = <2>;
4330 bias-pull-down;
4334 cam1_default: cam1-default-state {
4335 mclk-pins {
4338 drive-strength = <2>;
4339 bias-disable;
4343 cam1_sleep: cam1-sleep-state {
4344 mclk-pins {
4347 drive-strength = <2>;
4348 bias-pull-down;
4352 cam2_default: cam2-default-state {
4353 mclk-pins {
4356 drive-strength = <2>;
4357 bias-disable;
4361 cam2_sleep: cam2-sleep-state {
4362 mclk-pins {
4365 drive-strength = <2>;
4366 bias-pull-down;
4370 cam3_default: cam3-default-state {
4371 mclk-pins {
4374 drive-strength = <2>;
4375 bias-disable;
4379 cam3_sleep: cam3-sleep-state {
4380 mclk-pins {
4383 drive-strength = <2>;
4384 bias-pull-down;
4388 cam4_default: cam4-default-state {
4389 mclk-pins {
4392 drive-strength = <2>;
4393 bias-disable;
4397 cam4_sleep: cam4-sleep-state {
4398 mclk-pins {
4401 drive-strength = <2>;
4402 bias-pull-down;
4406 cam5_default: cam5-default-state {
4407 mclk-pins {
4410 drive-strength = <2>;
4411 bias-disable;
4415 cam5_sleep: cam5-sleep-state {
4416 mclk-pins {
4419 drive-strength = <2>;
4420 bias-pull-down;
4424 cam6_default: cam6-default-state {
4425 mclk-pins {
4428 drive-strength = <2>;
4429 bias-disable;
4433 cam6_sleep: cam6-sleep-state {
4434 mclk-pins {
4437 drive-strength = <2>;
4438 bias-pull-down;
4442 cam7_default: cam7-default-state {
4443 mclk-pins {
4446 drive-strength = <2>;
4447 bias-disable;
4451 cam7_sleep: cam7-sleep-state {
4452 mclk-pins {
4455 drive-strength = <2>;
4456 bias-pull-down;
4460 cci0_0_default: cci0-0-default-state {
4461 sda-pins {
4464 drive-strength = <2>;
4465 bias-pull-up = <2200>;
4468 scl-pins {
4471 drive-strength = <2>;
4472 bias-pull-up = <2200>;
4476 cci0_0_sleep: cci0-0-sleep-state {
4477 sda-pins {
4480 drive-strength = <2>;
4481 bias-pull-down;
4484 scl-pins {
4487 drive-strength = <2>;
4488 bias-pull-down;
4492 cci0_1_default: cci0-1-default-state {
4493 sda-pins {
4496 drive-strength = <2>;
4497 bias-pull-up = <2200>;
4500 scl-pins {
4503 drive-strength = <2>;
4504 bias-pull-up = <2200>;
4508 cci0_1_sleep: cci0-1-sleep-state {
4509 sda-pins {
4512 drive-strength = <2>;
4513 bias-pull-down;
4516 scl-pins {
4519 drive-strength = <2>;
4520 bias-pull-down;
4524 cci1_0_default: cci1-0-default-state {
4525 sda-pins {
4528 drive-strength = <2>;
4529 bias-pull-up = <2200>;
4532 scl-pins {
4535 drive-strength = <2>;
4536 bias-pull-up = <2200>;
4540 cci1_0_sleep: cci1-0-sleep-state {
4541 sda-pins {
4544 drive-strength = <2>;
4545 bias-pull-down;
4548 scl-pins {
4551 drive-strength = <2>;
4552 bias-pull-down;
4556 cci2_0_default: cci2-0-default-state {
4557 sda-pins {
4560 drive-strength = <2>;
4561 bias-pull-up = <2200>;
4564 scl-pins {
4567 drive-strength = <2>;
4568 bias-pull-up = <2200>;
4572 cci2_0_sleep: cci2-0-sleep-state {
4573 sda-pins {
4576 drive-strength = <2>;
4577 bias-pull-down;
4580 scl-pins {
4583 drive-strength = <2>;
4584 bias-pull-down;
4588 cci2_1_default: cci2-1-default-state {
4589 sda-pins {
4592 drive-strength = <2>;
4593 bias-pull-up = <2200>;
4596 scl-pins {
4599 drive-strength = <2>;
4600 bias-pull-up = <2200>;
4604 cci2_1_sleep: cci2-1-sleep-state {
4605 sda-pins {
4608 drive-strength = <2>;
4609 bias-pull-down;
4612 scl-pins {
4615 drive-strength = <2>;
4616 bias-pull-down;
4620 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
4624 drive-strength = <2>;
4625 bias-pull-up;
4628 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
4632 drive-strength = <2>;
4633 bias-pull-up;
4636 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
4640 drive-strength = <2>;
4641 bias-pull-up;
4644 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
4648 drive-strength = <2>;
4649 bias-pull-up;
4652 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
4656 drive-strength = <2>;
4657 bias-pull-up;
4660 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
4664 drive-strength = <2>;
4665 bias-pull-up;
4668 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
4672 drive-strength = <2>;
4673 bias-pull-up;
4676 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
4680 drive-strength = <2>;
4681 bias-pull-up;
4684 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
4688 drive-strength = <2>;
4689 bias-pull-up;
4692 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
4696 drive-strength = <2>;
4697 bias-pull-up;
4700 pcie0_default_state: pcie0-default-state {
4701 perst-pins {
4704 drive-strength = <2>;
4705 bias-pull-down;
4708 clkreq-pins {
4711 drive-strength = <2>;
4712 bias-pull-up;
4715 wake-pins {
4718 drive-strength = <2>;
4719 bias-pull-up;
4723 pcie1_default_state: pcie1-default-state {
4724 perst-pins {
4727 drive-strength = <2>;
4728 bias-pull-down;
4731 clkreq-pins {
4734 drive-strength = <2>;
4735 bias-pull-up;
4738 wake-pins {
4741 drive-strength = <2>;
4742 bias-pull-up;
4746 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4750 drive-strength = <2>;
4751 bias-pull-up = <2200>;
4754 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4758 drive-strength = <2>;
4759 bias-pull-up = <2200>;
4762 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4766 drive-strength = <2>;
4767 bias-pull-up = <2200>;
4770 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4774 drive-strength = <2>;
4775 bias-pull-up = <2200>;
4778 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4782 drive-strength = <2>;
4783 bias-pull-up = <2200>;
4786 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4790 drive-strength = <2>;
4791 bias-pull-up = <2200>;
4794 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4798 drive-strength = <2>;
4799 bias-pull-up = <2200>;
4802 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4803 scl-pins {
4806 drive-strength = <2>;
4807 bias-pull-up = <2200>;
4810 sda-pins {
4813 drive-strength = <2>;
4814 bias-pull-up = <2200>;
4818 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4822 drive-strength = <2>;
4823 bias-pull-up = <2200>;
4826 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4830 drive-strength = <2>;
4831 bias-pull-up = <2200>;
4834 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4838 drive-strength = <2>;
4839 bias-pull-up = <2200>;
4842 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4846 drive-strength = <2>;
4847 bias-pull-up = <2200>;
4850 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4854 drive-strength = <2>;
4855 bias-pull-up = <2200>;
4858 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4862 drive-strength = <2>;
4863 bias-pull-up = <2200>;
4866 qup_spi0_cs: qup-spi0-cs-state {
4869 drive-strength = <6>;
4870 bias-disable;
4873 qup_spi0_data_clk: qup-spi0-data-clk-state {
4877 drive-strength = <6>;
4878 bias-disable;
4881 qup_spi1_cs: qup-spi1-cs-state {
4884 drive-strength = <6>;
4885 bias-disable;
4888 qup_spi1_data_clk: qup-spi1-data-clk-state {
4892 drive-strength = <6>;
4893 bias-disable;
4896 qup_spi2_cs: qup-spi2-cs-state {
4899 drive-strength = <6>;
4900 bias-disable;
4903 qup_spi2_data_clk: qup-spi2-data-clk-state {
4907 drive-strength = <6>;
4908 bias-disable;
4911 qup_spi3_cs: qup-spi3-cs-state {
4914 drive-strength = <6>;
4915 bias-disable;
4918 qup_spi3_data_clk: qup-spi3-data-clk-state {
4922 drive-strength = <6>;
4923 bias-disable;
4926 qup_spi4_cs: qup-spi4-cs-state {
4929 drive-strength = <6>;
4930 bias-disable;
4933 qup_spi4_data_clk: qup-spi4-data-clk-state {
4937 drive-strength = <6>;
4938 bias-disable;
4941 qup_spi5_cs: qup-spi5-cs-state {
4944 drive-strength = <6>;
4945 bias-disable;
4948 qup_spi5_data_clk: qup-spi5-data-clk-state {
4952 drive-strength = <6>;
4953 bias-disable;
4956 qup_spi6_cs: qup-spi6-cs-state {
4959 drive-strength = <6>;
4960 bias-disable;
4963 qup_spi6_data_clk: qup-spi6-data-clk-state {
4967 drive-strength = <6>;
4968 bias-disable;
4971 qup_spi8_cs: qup-spi8-cs-state {
4974 drive-strength = <6>;
4975 bias-disable;
4978 qup_spi8_data_clk: qup-spi8-data-clk-state {
4982 drive-strength = <6>;
4983 bias-disable;
4986 qup_spi9_cs: qup-spi9-cs-state {
4989 drive-strength = <6>;
4990 bias-disable;
4993 qup_spi9_data_clk: qup-spi9-data-clk-state {
4997 drive-strength = <6>;
4998 bias-disable;
5001 qup_spi10_cs: qup-spi10-cs-state {
5004 drive-strength = <6>;
5005 bias-disable;
5008 qup_spi10_data_clk: qup-spi10-data-clk-state {
5012 drive-strength = <6>;
5013 bias-disable;
5016 qup_spi11_cs: qup-spi11-cs-state {
5019 drive-strength = <6>;
5020 bias-disable;
5023 qup_spi11_data_clk: qup-spi11-data-clk-state {
5027 drive-strength = <6>;
5028 bias-disable;
5031 qup_spi12_cs: qup-spi12-cs-state {
5034 drive-strength = <6>;
5035 bias-disable;
5038 qup_spi12_data_clk: qup-spi12-data-clk-state {
5042 drive-strength = <6>;
5043 bias-disable;
5046 qup_spi13_cs: qup-spi13-cs-state {
5049 drive-strength = <6>;
5050 bias-disable;
5053 qup_spi13_data_clk: qup-spi13-data-clk-state {
5057 drive-strength = <6>;
5058 bias-disable;
5061 qup_spi15_cs: qup-spi15-cs-state {
5064 drive-strength = <6>;
5065 bias-disable;
5068 qup_spi15_data_clk: qup-spi15-data-clk-state {
5072 drive-strength = <6>;
5073 bias-disable;
5076 qup_uart7_default: qup-uart7-default-state {
5080 drive-strength = <2>;
5081 bias-disable;
5084 qup_uart14_default: qup-uart14-default-state {
5088 drive-strength = <2>;
5089 bias-pull-up;
5092 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
5096 drive-strength = <2>;
5097 bias-pull-down;
5100 sdc2_sleep: sdc2-sleep-state {
5101 clk-pins {
5103 bias-disable;
5104 drive-strength = <2>;
5107 cmd-pins {
5109 bias-pull-up;
5110 drive-strength = <2>;
5113 data-pins {
5115 bias-pull-up;
5116 drive-strength = <2>;
5120 sdc2_default: sdc2-default-state {
5121 clk-pins {
5123 bias-disable;
5124 drive-strength = <16>;
5127 cmd-pins {
5129 bias-pull-up;
5130 drive-strength = <10>;
5133 data-pins {
5135 bias-pull-up;
5136 drive-strength = <10>;
5142 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5144 #iommu-cells = <2>;
5145 #global-interrupts = <1>;
5243 dma-coherent;
5246 intc: interrupt-controller@17100000 {
5247 compatible = "arm,gic-v3";
5251 #interrupt-cells = <4>;
5252 interrupt-controller;
5253 #redistributor-regions = <1>;
5254 redistributor-stride = <0 0x40000>;
5256 #address-cells = <2>;
5257 #size-cells = <2>;
5259 ppi-partitions {
5260 ppi_cluster0: interrupt-partition-0 {
5264 ppi_cluster1: interrupt-partition-1 {
5268 ppi_cluster2: interrupt-partition-2 {
5272 ppi_cluster3: interrupt-partition-3 {
5277 gic_its: msi-controller@17140000 {
5278 compatible = "arm,gic-v3-its";
5280 msi-controller;
5281 #msi-cells = <1>;
5286 compatible = "arm,armv7-timer-mem";
5289 #address-cells = <1>;
5290 #size-cells = <1>;
5295 frame-number = <0>;
5302 frame-number = <1>;
5309 frame-number = <2>;
5316 frame-number = <3>;
5323 frame-number = <4>;
5330 frame-number = <5>;
5337 frame-number = <6>;
5345 compatible = "qcom,rpmh-rsc";
5350 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5354 qcom,tcs-offset = <0xd00>;
5355 qcom,drv-id = <2>;
5356 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5358 power-domains = <&cluster_pd>;
5360 apps_bcm_voter: bcm-voter {
5361 compatible = "qcom,bcm-voter";
5364 rpmhcc: clock-controller {
5365 compatible = "qcom,sm8550-rpmh-clk";
5366 #clock-cells = <1>;
5367 clock-names = "xo";
5371 rpmhpd: power-controller {
5372 compatible = "qcom,sm8550-rpmhpd";
5373 #power-domain-cells = <1>;
5374 operating-points-v2 = <&rpmhpd_opp_table>;
5376 rpmhpd_opp_table: opp-table {
5377 compatible = "operating-points-v2";
5379 rpmhpd_opp_ret: opp-16 {
5380 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5383 rpmhpd_opp_min_svs: opp-48 {
5384 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5387 rpmhpd_opp_low_svs_d2: opp-52 {
5388 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5391 rpmhpd_opp_low_svs_d1: opp-56 {
5392 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5395 rpmhpd_opp_low_svs_d0: opp-60 {
5396 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5399 rpmhpd_opp_low_svs: opp-64 {
5400 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5403 rpmhpd_opp_low_svs_l1: opp-80 {
5404 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5407 rpmhpd_opp_svs: opp-128 {
5408 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5411 rpmhpd_opp_svs_l0: opp-144 {
5412 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5415 rpmhpd_opp_svs_l1: opp-192 {
5416 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5419 rpmhpd_opp_nom: opp-256 {
5420 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5423 rpmhpd_opp_nom_l1: opp-320 {
5424 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5427 rpmhpd_opp_nom_l2: opp-336 {
5428 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5431 rpmhpd_opp_turbo: opp-384 {
5432 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5435 rpmhpd_opp_turbo_l1: opp-416 {
5436 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5443 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
5447 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
5448 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
5449 clock-names = "xo", "alternate";
5453 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5454 #freq-domain-cells = <1>;
5455 #clock-cells = <1>;
5459 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5465 operating-points-v2 = <&llcc_bwmon_opp_table>;
5467 llcc_bwmon_opp_table: opp-table {
5468 compatible = "operating-points-v2";
5470 opp-0 {
5471 opp-peak-kBps = <2086000>;
5474 opp-1 {
5475 opp-peak-kBps = <2929000>;
5478 opp-2 {
5479 opp-peak-kBps = <5931000>;
5482 opp-3 {
5483 opp-peak-kBps = <6515000>;
5486 opp-4 {
5487 opp-peak-kBps = <7980000>;
5490 opp-5 {
5491 opp-peak-kBps = <10437000>;
5494 opp-6 {
5495 opp-peak-kBps = <12157000>;
5498 opp-7 {
5499 opp-peak-kBps = <14060000>;
5502 opp-8 {
5503 opp-peak-kBps = <16113000>;
5509 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
5515 operating-points-v2 = <&cpu_bwmon_opp_table>;
5517 cpu_bwmon_opp_table: opp-table {
5518 compatible = "operating-points-v2";
5520 opp-0 {
5521 opp-peak-kBps = <4577000>;
5524 opp-1 {
5525 opp-peak-kBps = <7110000>;
5528 opp-2 {
5529 opp-peak-kBps = <9155000>;
5532 opp-3 {
5533 opp-peak-kBps = <12298000>;
5536 opp-4 {
5537 opp-peak-kBps = <14236000>;
5540 opp-5 {
5541 opp-peak-kBps = <16265000>;
5547 compatible = "qcom,sm8550-gem-noc";
5549 #interconnect-cells = <2>;
5550 qcom,bcm-voters = <&apps_bcm_voter>;
5553 system-cache-controller@25000000 {
5554 compatible = "qcom,sm8550-llcc";
5561 reg-names = "llcc0_base",
5571 compatible = "qcom,sm8550-nsp-noc";
5573 #interconnect-cells = <2>;
5574 qcom,bcm-voters = <&apps_bcm_voter>;
5578 compatible = "qcom,sm8550-cdsp-pas";
5581 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
5586 interrupt-names = "wdog", "fatal", "ready",
5587 "handover", "stop-ack";
5590 clock-names = "xo";
5592 power-domains = <&rpmhpd RPMHPD_CX>,
5595 power-domain-names = "cx", "mxc", "nsp";
5600 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
5604 qcom,smem-states = <&smp2p_cdsp_out 0>;
5605 qcom,smem-state-names = "stop";
5609 glink-edge {
5610 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5617 qcom,remote-pid = <5>;
5621 qcom,glink-channels = "fastrpcglink-apps-dsp";
5623 qcom,non-secure-domain;
5624 #address-cells = <1>;
5625 #size-cells = <0>;
5627 compute-cb@1 {
5628 compatible = "qcom,fastrpc-compute-cb";
5633 dma-coherent;
5636 compute-cb@2 {
5637 compatible = "qcom,fastrpc-compute-cb";
5642 dma-coherent;
5645 compute-cb@3 {
5646 compatible = "qcom,fastrpc-compute-cb";
5651 dma-coherent;
5654 compute-cb@4 {
5655 compatible = "qcom,fastrpc-compute-cb";
5660 dma-coherent;
5663 compute-cb@5 {
5664 compatible = "qcom,fastrpc-compute-cb";
5669 dma-coherent;
5672 compute-cb@6 {
5673 compatible = "qcom,fastrpc-compute-cb";
5678 dma-coherent;
5681 compute-cb@7 {
5682 compatible = "qcom,fastrpc-compute-cb";
5687 dma-coherent;
5690 compute-cb@8 {
5691 compatible = "qcom,fastrpc-compute-cb";
5696 dma-coherent;
5705 thermal-zones {
5706 aoss0-thermal {
5707 thermal-sensors = <&tsens0 0>;
5710 thermal-engine-config {
5716 reset-mon-config {
5724 cpuss0-thermal {
5725 thermal-sensors = <&tsens0 1>;
5728 thermal-engine-config {
5734 reset-mon-config {
5742 cpuss1-thermal {
5743 thermal-sensors = <&tsens0 2>;
5746 thermal-engine-config {
5752 reset-mon-config {
5760 cpuss2-thermal {
5761 thermal-sensors = <&tsens0 3>;
5764 thermal-engine-config {
5770 reset-mon-config {
5778 cpuss3-thermal {
5779 thermal-sensors = <&tsens0 4>;
5782 thermal-engine-config {
5788 reset-mon-config {
5796 cpu3-top-thermal {
5797 thermal-sensors = <&tsens0 5>;
5800 cpu3_top_alert0: trip-point0 {
5806 cpu3_top_alert1: trip-point1 {
5812 cpu3_top_crit: cpu-critical {
5820 cpu3-bottom-thermal {
5821 thermal-sensors = <&tsens0 6>;
5824 cpu3_bottom_alert0: trip-point0 {
5830 cpu3_bottom_alert1: trip-point1 {
5836 cpu3_bottom_crit: cpu-critical {
5844 cpu4-top-thermal {
5845 thermal-sensors = <&tsens0 7>;
5848 cpu4_top_alert0: trip-point0 {
5854 cpu4_top_alert1: trip-point1 {
5860 cpu4_top_crit: cpu-critical {
5868 cpu4-bottom-thermal {
5869 thermal-sensors = <&tsens0 8>;
5872 cpu4_bottom_alert0: trip-point0 {
5878 cpu4_bottom_alert1: trip-point1 {
5884 cpu4_bottom_crit: cpu-critical {
5892 cpu5-top-thermal {
5893 thermal-sensors = <&tsens0 9>;
5896 cpu5_top_alert0: trip-point0 {
5902 cpu5_top_alert1: trip-point1 {
5908 cpu5_top_crit: cpu-critical {
5916 cpu5-bottom-thermal {
5917 thermal-sensors = <&tsens0 10>;
5920 cpu5_bottom_alert0: trip-point0 {
5926 cpu5_bottom_alert1: trip-point1 {
5932 cpu5_bottom_crit: cpu-critical {
5940 cpu6-top-thermal {
5941 thermal-sensors = <&tsens0 11>;
5944 cpu6_top_alert0: trip-point0 {
5950 cpu6_top_alert1: trip-point1 {
5956 cpu6_top_crit: cpu-critical {
5964 cpu6-bottom-thermal {
5965 thermal-sensors = <&tsens0 12>;
5968 cpu6_bottom_alert0: trip-point0 {
5974 cpu6_bottom_alert1: trip-point1 {
5980 cpu6_bottom_crit: cpu-critical {
5988 cpu7-top-thermal {
5989 thermal-sensors = <&tsens0 13>;
5992 cpu7_top_alert0: trip-point0 {
5998 cpu7_top_alert1: trip-point1 {
6004 cpu7_top_crit: cpu-critical {
6012 cpu7-middle-thermal {
6013 thermal-sensors = <&tsens0 14>;
6016 cpu7_middle_alert0: trip-point0 {
6022 cpu7_middle_alert1: trip-point1 {
6028 cpu7_middle_crit: cpu-critical {
6036 cpu7-bottom-thermal {
6037 thermal-sensors = <&tsens0 15>;
6040 cpu7_bottom_alert0: trip-point0 {
6046 cpu7_bottom_alert1: trip-point1 {
6052 cpu7_bottom_crit: cpu-critical {
6060 aoss1-thermal {
6061 thermal-sensors = <&tsens1 0>;
6064 thermal-engine-config {
6070 reset-mon-config {
6078 cpu0-thermal {
6079 thermal-sensors = <&tsens1 1>;
6082 cpu0_alert0: trip-point0 {
6088 cpu0_alert1: trip-point1 {
6094 cpu0_crit: cpu-critical {
6102 cpu1-thermal {
6103 thermal-sensors = <&tsens1 2>;
6106 cpu1_alert0: trip-point0 {
6112 cpu1_alert1: trip-point1 {
6118 cpu1_crit: cpu-critical {
6126 cpu2-thermal {
6127 thermal-sensors = <&tsens1 3>;
6130 cpu2_alert0: trip-point0 {
6136 cpu2_alert1: trip-point1 {
6142 cpu2_crit: cpu-critical {
6150 cdsp0-thermal {
6151 polling-delay-passive = <10>;
6153 thermal-sensors = <&tsens2 4>;
6156 thermal-engine-config {
6162 thermal-hal-config {
6168 reset-mon-config {
6174 cdsp0_junction_config: junction-config {
6182 cdsp1-thermal {
6183 polling-delay-passive = <10>;
6185 thermal-sensors = <&tsens2 5>;
6188 thermal-engine-config {
6194 thermal-hal-config {
6200 reset-mon-config {
6206 cdsp1_junction_config: junction-config {
6214 cdsp2-thermal {
6215 polling-delay-passive = <10>;
6217 thermal-sensors = <&tsens2 6>;
6220 thermal-engine-config {
6226 thermal-hal-config {
6232 reset-mon-config {
6238 cdsp2_junction_config: junction-config {
6246 cdsp3-thermal {
6247 polling-delay-passive = <10>;
6249 thermal-sensors = <&tsens2 7>;
6252 thermal-engine-config {
6258 thermal-hal-config {
6264 reset-mon-config {
6270 cdsp3_junction_config: junction-config {
6278 video-thermal {
6279 thermal-sensors = <&tsens1 8>;
6282 thermal-engine-config {
6288 reset-mon-config {
6296 mem-thermal {
6297 polling-delay-passive = <10>;
6299 thermal-sensors = <&tsens1 9>;
6302 thermal-engine-config {
6308 ddr_config0: ddr0-config {
6314 reset-mon-config {
6322 modem0-thermal {
6323 thermal-sensors = <&tsens1 10>;
6326 thermal-engine-config {
6332 mdmss0_config0: mdmss0-config0 {
6338 mdmss0_config1: mdmss0-config1 {
6344 reset-mon-config {
6352 modem1-thermal {
6353 thermal-sensors = <&tsens1 11>;
6356 thermal-engine-config {
6362 mdmss1_config0: mdmss1-config0 {
6368 mdmss1_config1: mdmss1-config1 {
6374 reset-mon-config {
6382 modem2-thermal {
6383 thermal-sensors = <&tsens1 12>;
6386 thermal-engine-config {
6392 mdmss2_config0: mdmss2-config0 {
6398 mdmss2_config1: mdmss2-config1 {
6404 reset-mon-config {
6412 modem3-thermal {
6413 thermal-sensors = <&tsens1 13>;
6416 thermal-engine-config {
6422 mdmss3_config0: mdmss3-config0 {
6428 mdmss3_config1: mdmss3-config1 {
6434 reset-mon-config {
6442 camera0-thermal {
6443 thermal-sensors = <&tsens1 14>;
6446 thermal-engine-config {
6452 reset-mon-config {
6460 camera1-thermal {
6461 thermal-sensors = <&tsens1 15>;
6464 thermal-engine-config {
6470 reset-mon-config {
6478 aoss2-thermal {
6479 thermal-sensors = <&tsens2 0>;
6482 thermal-engine-config {
6488 reset-mon-config {
6496 gpuss-0-thermal {
6497 polling-delay-passive = <10>;
6499 thermal-sensors = <&tsens2 1>;
6501 cooling-maps {
6504 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6509 gpu0_alert0: trip-point0 {
6515 trip-point1 {
6521 trip-point2 {
6529 gpuss-1-thermal {
6530 polling-delay-passive = <10>;
6532 thermal-sensors = <&tsens2 2>;
6534 cooling-maps {
6537 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6542 gpu1_alert0: trip-point0 {
6548 trip-point1 {
6554 trip-point2 {
6562 gpuss-2-thermal {
6563 polling-delay-passive = <10>;
6565 thermal-sensors = <&tsens2 3>;
6567 cooling-maps {
6570 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6575 gpu2_alert0: trip-point0 {
6581 trip-point1 {
6587 trip-point2 {
6595 gpuss-3-thermal {
6596 polling-delay-passive = <10>;
6598 thermal-sensors = <&tsens2 4>;
6600 cooling-maps {
6603 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6608 gpu3_alert0: trip-point0 {
6614 trip-point1 {
6620 trip-point2 {
6628 gpuss-4-thermal {
6629 polling-delay-passive = <10>;
6631 thermal-sensors = <&tsens2 5>;
6633 cooling-maps {
6636 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6641 gpu4_alert0: trip-point0 {
6647 trip-point1 {
6653 trip-point2 {
6661 gpuss-5-thermal {
6662 polling-delay-passive = <10>;
6664 thermal-sensors = <&tsens2 6>;
6666 cooling-maps {
6669 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6674 gpu5_alert0: trip-point0 {
6680 trip-point1 {
6686 trip-point2 {
6694 gpuss-6-thermal {
6695 polling-delay-passive = <10>;
6697 thermal-sensors = <&tsens2 7>;
6699 cooling-maps {
6702 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6707 gpu6_alert0: trip-point0 {
6713 trip-point1 {
6719 trip-point2 {
6727 gpuss-7-thermal {
6728 polling-delay-passive = <10>;
6730 thermal-sensors = <&tsens2 8>;
6732 cooling-maps {
6735 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6740 gpu7_alert0: trip-point0 {
6746 trip-point1 {
6752 trip-point2 {
6762 compatible = "arm,armv8-timer";