Lines Matching +full:1 +full:d84000
189 qcom,client-id = <1>;
303 clocks = <&cpufreq_hw 1>;
313 qcom,freq-domain = <&cpufreq_hw 1>;
327 clocks = <&cpufreq_hw 1>;
337 qcom,freq-domain = <&cpufreq_hw 1>;
351 clocks = <&cpufreq_hw 1>;
361 qcom,freq-domain = <&cpufreq_hw 1>;
444 little_cpu_sleep_1: cpu-sleep-0-1 {
454 big_cpu_sleep_0: cpu-sleep-1-0 {
464 big_cpu_sleep_1: cpu-sleep-1-1 {
484 cluster_sleep_cx_ret: cluster-sleep-1 {
746 #qcom,smem-state-cells = <1>;
770 #qcom,smem-state-cells = <1>;
790 qcom,remote-pid = <1>;
794 #qcom,smem-state-cells = <1>;
805 #qcom,smem-state-cells = <1>;
829 #qcom,smem-state-cells = <1>;
840 #qcom,smem-state-cells = <1>;
974 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
981 #clock-cells = <1>;
982 #reset-cells = <1>;
983 #power-domain-cells = <1>;
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1008 gpu_speed_bin: gpu-speed-bin@1e9 {
1018 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1047 mmc-ddr-1_8v;
1048 mmc-hs200-1_8v;
1049 mmc-hs400-1_8v;
1115 #address-cells = <1>;
1125 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1138 #address-cells = <1>;
1146 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1175 #address-cells = <1>;
1184 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1185 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1198 #address-cells = <1>;
1205 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1206 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1235 #address-cells = <1>;
1245 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1258 #address-cells = <1>;
1266 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1295 #address-cells = <1>;
1305 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1318 #address-cells = <1>;
1326 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1355 #address-cells = <1>;
1365 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1378 #address-cells = <1>;
1386 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1415 #address-cells = <1>;
1425 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1438 #address-cells = <1>;
1446 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1475 #address-cells = <1>;
1485 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1498 #address-cells = <1>;
1506 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1535 #address-cells = <1>;
1545 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1558 #address-cells = <1>;
1566 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1630 #address-cells = <1>;
1640 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1653 #address-cells = <1>;
1661 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1690 #address-cells = <1>;
1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1700 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1713 #address-cells = <1>;
1720 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1721 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1750 #address-cells = <1>;
1760 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1773 #address-cells = <1>;
1781 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1810 #address-cells = <1>;
1820 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1833 #address-cells = <1>;
1841 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1870 #address-cells = <1>;
1880 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1893 #address-cells = <1>;
1901 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1930 #address-cells = <1>;
1940 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1953 #address-cells = <1>;
1961 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1990 #address-cells = <1>;
2000 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2013 #address-cells = <1>;
2021 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2050 #address-cells = <1>;
2060 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2073 #address-cells = <1>;
2081 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2203 pcie1: pcie@1c08000 {
2213 linux,pci-domain = <1>;
2241 #interrupt-cells = <1>;
2243 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2308 pcie1_phy: phy@1c0e000 {
2336 ufs_mem_hc: ufshc@1d84000 {
2344 #reset-cells = <1>;
2424 ufs_mem_phy: phy@1d87000 {
2437 #clock-cells = <1>;
2443 ice: crypto@1d88000 {
2450 cryptobam: dma-controller@1dc4000 {
2454 #dma-cells = <1>;
2463 crypto: crypto@1dfa000 {
2474 ipa: ipa@1e40000 {
2489 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2506 <&ipa_smp2p_out 1>;
2513 tcsr_mutex: hwlock@1f40000 {
2516 #hwlock-cells = <1>;
2519 tcsr_1: syscon@1f60000 {
2524 tcsr_2: syscon@1fc0000 {
2536 #clock-cells = <1>;
2557 #sound-dai-cells = <1>;
2586 #sound-dai-cells = <1>;
2610 #sound-dai-cells = <1>;
2640 #sound-dai-cells = <1>;
2655 #clock-cells = <1>;
2656 #power-domain-cells = <1>;
2657 #reset-cells = <1>;
2672 #sound-dai-cells = <1>;
2684 #clock-cells = <1>;
2685 #power-domain-cells = <1>;
2695 #clock-cells = <1>;
2696 #power-domain-cells = <1>;
2745 #sound-dai-cells = <1>;
2746 #address-cells = <1>;
2765 #dma-cells = <1>;
2768 qcom,ee = <1>;
2781 #address-cells = <1>;
2791 #clock-cells = <1>;
2792 #power-domain-cells = <1>;
2862 <&adreno_smmu 1 0x400>;
2903 opp-550000000-1 {
2996 #clock-cells = <1>;
2997 #reset-cells = <1>;
2998 #power-domain-cells = <1>;
3063 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3093 qcom,remote-pid = <1>;
3131 #address-cells = <1>;
3159 #address-cells = <1>;
3187 #address-cells = <1>;
3197 port@1 {
3198 reg = <1>;
3264 #address-cells = <1>;
3501 #address-cells = <1>;
3511 port@1 {
3512 reg = <1>;
3590 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3680 #clock-cells = <1>;
3681 #phy-cells = <1>;
3686 #address-cells = <1>;
3696 port@1 {
3697 reg = <1>;
3782 #address-cells = <1>;
3802 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3840 #address-cells = <1>;
3856 #address-cells = <1>;
3858 #sound-dai-cells = <1>;
3874 #address-cells = <1>;
3876 #sound-dai-cells = <1>;
3883 dai@1 {
3910 #address-cells = <1>;
3943 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3995 opp-1 {
4034 opp-1 {
4086 #address-cells = <1>;
4111 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4151 #address-cells = <1>;
4154 compute-cb@1 {
4156 reg = <1>;
4316 #address-cells = <1>;
4326 port@1 {
4327 reg = <1>;
4401 #clock-cells = <1>;
4402 #reset-cells = <1>;
4403 #power-domain-cells = <1>;
4423 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4426 #address-cells = <1>;
4434 #address-cells = <1>;
4438 cci0_i2c1: i2c-bus@1 {
4439 reg = <1>;
4441 #address-cells = <1>;
4463 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4466 #address-cells = <1>;
4474 #address-cells = <1>;
4478 cci1_i2c1: i2c-bus@1 {
4479 reg = <1>;
4481 #address-cells = <1>;
4639 #address-cells = <1>;
4646 port@1 {
4647 reg = <1>;
4671 #clock-cells = <1>;
4672 #reset-cells = <1>;
4673 #power-domain-cells = <1>;
4686 <&mdss_edp_phy 1>;
4695 #clock-cells = <1>;
4696 #reset-cells = <1>;
4697 #power-domain-cells = <1>;
4716 #interrupt-cells = <1>;
4762 #address-cells = <1>;
4772 port@1 {
4773 reg = <1>;
4849 #address-cells = <1>;
4855 #address-cells = <1>;
4865 port@1 {
4866 reg = <1>;
4901 #clock-cells = <1>;
4936 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4947 #address-cells = <1>;
4957 port@1 {
4958 reg = <1>;
5001 #clock-cells = <1>;
5044 #address-cells = <1>;
5054 port@1 {
5055 reg = <1>;
5091 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
5093 <64 434 2>, <66 438 3>, <69 86 1>,
5094 <70 520 54>, <124 609 31>, <155 63 1>,
5104 #reset-cells = <1>;
5116 #thermal-sensor-cells = <1>;
5127 #thermal-sensor-cells = <1>;
5133 #reset-cells = <1>;
5162 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
6028 #address-cells = <1>;
6029 #size-cells = <1>;
6043 #global-interrupts = <1>;
6220 #msi-cells = <1>;
6234 #address-cells = <1>;
6235 #size-cells = <1>;
6249 frame-number = <1>;
6296 reg-names = "drv-0", "drv-1", "drv-2";
6305 <CONTROL_TCS 1>;
6314 #power-domain-cells = <1>;
6362 #clock-cells = <1>;
6371 #interconnect-cells = <1>;
6384 "dcvsh-irq-1",
6389 #freq-domain-cells = <1>;
6390 #clock-cells = <1>;
6401 thermal-sensors = <&tsens0 1>;
6995 thermal-sensors = <&tsens1 1>;