Lines Matching +full:ipq9574 +full:- +full:gcc
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ9574 SoC device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interconnect/qcom,ipq9574.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 sleep_clk: sleep-clk {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
27 xo_board_clk: xo-board-clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a73";
41 enable-method = "psci";
42 next-level-cache = <&l2_0>;
44 clock-names = "cpu";
45 operating-points-v2 = <&cpu_opp_table>;
46 cpu-supply = <&ipq9574_s1>;
47 #cooling-cells = <2>;
52 compatible = "arm,cortex-a73";
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
57 clock-names = "cpu";
58 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a73";
67 enable-method = "psci";
68 next-level-cache = <&l2_0>;
70 clock-names = "cpu";
71 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a73";
80 enable-method = "psci";
81 next-level-cache = <&l2_0>;
83 clock-names = "cpu";
84 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>;
89 l2_0: l2-cache {
91 cache-level = <2>;
92 cache-unified;
98 compatible = "qcom,scm-ipq9574", "qcom,scm";
99 qcom,dload-mode = <&tcsr 0x6100>;
109 cpu_opp_table: opp-table-cpu {
110 compatible = "operating-points-v2-kryo-cpu";
111 opp-shared;
112 nvmem-cells = <&cpu_speed_bin>;
114 opp-936000000 {
115 opp-hz = /bits/ 64 <936000000>;
116 opp-microvolt = <725000>;
117 opp-supported-hw = <0xf>;
118 clock-latency-ns = <200000>;
121 opp-1104000000 {
122 opp-hz = /bits/ 64 <1104000000>;
123 opp-microvolt = <787500>;
124 opp-supported-hw = <0xf>;
125 clock-latency-ns = <200000>;
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <862500>;
131 opp-supported-hw = <0xf>;
132 clock-latency-ns = <200000>;
135 opp-1416000000 {
136 opp-hz = /bits/ 64 <1416000000>;
137 opp-microvolt = <862500>;
138 opp-supported-hw = <0x7>;
139 clock-latency-ns = <200000>;
142 opp-1488000000 {
143 opp-hz = /bits/ 64 <1488000000>;
144 opp-microvolt = <925000>;
145 opp-supported-hw = <0x7>;
146 clock-latency-ns = <200000>;
149 opp-1800000000 {
150 opp-hz = /bits/ 64 <1800000000>;
151 opp-microvolt = <987500>;
152 opp-supported-hw = <0x5>;
153 clock-latency-ns = <200000>;
156 opp-2208000000 {
157 opp-hz = /bits/ 64 <2208000000>;
158 opp-microvolt = <1062500>;
159 opp-supported-hw = <0x1>;
160 clock-latency-ns = <200000>;
165 compatible = "arm,cortex-a73-pmu";
170 compatible = "arm,psci-1.0";
175 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
177 glink-edge {
178 compatible = "qcom,glink-rpm";
180 qcom,rpm-msg-ram = <&rpm_msg_ram>;
183 rpm_requests: rpm-requests {
184 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
185 qcom,glink-channels = "rpm_requests";
190 reserved-memory {
191 #address-cells = <2>;
192 #size-cells = <2>;
197 no-map;
202 no-map;
207 no-map;
214 no-map;
219 compatible = "simple-bus";
220 #address-cells = <1>;
221 #size-cells = <1>;
225 compatible = "qcom,rpm-msg-ram";
230 compatible = "qcom,prng-ee";
232 clocks = <&gcc GCC_PRNG_AHB_CLK>;
233 clock-names = "core";
237 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&gcc GCC_MDIO_AHB_CLK>;
242 clock-names = "gcc_mdio_ahb_clk";
247 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
249 #address-cells = <1>;
250 #size-cells = <1>;
252 cpu_speed_bin: cpu-speed-bin@15 {
258 cryptobam: dma-controller@704000 {
259 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
262 #dma-cells = <1>;
264 qcom,controlled-remotely;
268 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
270 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 <&gcc GCC_CRYPTO_AXI_CLK>,
272 <&gcc GCC_CRYPTO_CLK>;
273 clock-names = "iface", "bus", "core";
275 dma-names = "rx", "tx";
278 tsens: thermal-sensor@4a9000 {
279 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
283 interrupt-names = "combined";
285 #thermal-sensor-cells = <1>;
289 compatible = "qcom,ipq9574-tlmm";
292 gpio-controller;
293 #gpio-cells = <2>;
294 gpio-ranges = <&tlmm 0 0 65>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
298 uart2_pins: uart2-state {
301 drive-strength = <8>;
302 bias-disable;
306 gcc: clock-controller@1800000 { label
307 compatible = "qcom,ipq9574-gcc";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 #interconnect-cells = <1>;
323 compatible = "qcom,tcsr-mutex";
325 #hwlock-cells = <1>;
329 compatible = "qcom,tcsr-ipq9574", "syscon";
334 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
338 reg-names = "hc", "cqhci", "ice";
342 interrupt-names = "hc_irq", "pwr_irq";
344 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 <&gcc GCC_SDCC1_APPS_CLK>,
347 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
348 clock-names = "iface", "core", "xo", "ice";
349 non-removable;
350 supports-cqe;
354 blsp_dma: dma-controller@7884000 {
355 compatible = "qcom,bam-v1.7.0";
358 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
359 clock-names = "bam_clk";
360 #dma-cells = <1>;
365 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
368 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 <&gcc GCC_BLSP1_AHB_CLK>;
370 clock-names = "core", "iface";
375 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
378 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 <&gcc GCC_BLSP1_AHB_CLK>;
380 clock-names = "core", "iface";
385 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
388 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", "iface";
395 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
398 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", "iface";
405 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
408 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 <&gcc GCC_BLSP1_AHB_CLK>;
410 clock-names = "core", "iface";
415 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
418 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 <&gcc GCC_BLSP1_AHB_CLK>;
420 clock-names = "core", "iface";
425 compatible = "qcom,spi-qup-v2.2.1";
427 #address-cells = <1>;
428 #size-cells = <0>;
430 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", "iface";
434 dma-names = "tx", "rx";
439 compatible = "qcom,i2c-qup-v2.2.1";
441 #address-cells = <1>;
442 #size-cells = <0>;
444 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 <&gcc GCC_BLSP1_AHB_CLK>;
446 clock-names = "core", "iface";
447 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
448 assigned-clock-rates = <50000000>;
450 dma-names = "tx", "rx";
455 compatible = "qcom,spi-qup-v2.2.1";
457 #address-cells = <1>;
458 #size-cells = <0>;
460 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 <&gcc GCC_BLSP1_AHB_CLK>;
462 clock-names = "core", "iface";
464 dma-names = "tx", "rx";
469 compatible = "qcom,i2c-qup-v2.2.1";
471 #address-cells = <1>;
472 #size-cells = <0>;
474 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 <&gcc GCC_BLSP1_AHB_CLK>;
476 clock-names = "core", "iface";
477 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
478 assigned-clock-rates = <50000000>;
480 dma-names = "tx", "rx";
485 compatible = "qcom,spi-qup-v2.2.1";
487 #address-cells = <1>;
488 #size-cells = <0>;
490 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 <&gcc GCC_BLSP1_AHB_CLK>;
492 clock-names = "core", "iface";
494 dma-names = "tx", "rx";
499 compatible = "qcom,i2c-qup-v2.2.1";
501 #address-cells = <1>;
502 #size-cells = <0>;
504 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 <&gcc GCC_BLSP1_AHB_CLK>;
506 clock-names = "core", "iface";
507 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
508 assigned-clock-rates = <50000000>;
510 dma-names = "tx", "rx";
515 compatible = "qcom,spi-qup-v2.2.1";
517 #address-cells = <1>;
518 #size-cells = <0>;
520 spi-max-frequency = <50000000>;
521 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", "iface";
525 dma-names = "tx", "rx";
530 compatible = "qcom,i2c-qup-v2.2.1";
532 #address-cells = <1>;
533 #size-cells = <0>;
535 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", "iface";
538 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
539 assigned-clock-rates = <50000000>;
541 dma-names = "tx", "rx";
546 compatible = "qcom,spi-qup-v2.2.1";
548 #address-cells = <1>;
549 #size-cells = <0>;
551 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 <&gcc GCC_BLSP1_AHB_CLK>;
553 clock-names = "core", "iface";
555 dma-names = "tx", "rx";
560 compatible = "qcom,ipq9574-qusb2-phy";
562 #phy-cells = <0>;
564 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
566 clock-names = "cfg_ahb",
569 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
574 compatible = "qcom,ipq9574-qmp-usb3-phy";
576 #phy-cells = <0>;
578 clocks = <&gcc GCC_USB0_AUX_CLK>,
580 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
581 <&gcc GCC_USB0_PIPE_CLK>;
582 clock-names = "aux",
587 resets = <&gcc GCC_USB0_PHY_BCR>,
588 <&gcc GCC_USB3PHY_0_PHY_BCR>;
589 reset-names = "phy",
592 #clock-cells = <0>;
593 clock-output-names = "usb0_pipe_clk";
599 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
601 #address-cells = <1>;
602 #size-cells = <1>;
605 clocks = <&gcc GCC_SNOC_USB_CLK>,
606 <&gcc GCC_USB0_MASTER_CLK>,
607 <&gcc GCC_ANOC_USB_AXI_CLK>,
608 <&gcc GCC_USB0_SLEEP_CLK>,
609 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
611 clock-names = "cfg_noc",
617 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
618 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
619 assigned-clock-rates = <200000000>,
622 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "pwr_event";
625 resets = <&gcc GCC_USB_BCR>;
631 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
632 clock-names = "ref";
635 phy-names = "usb2-phy", "usb3-phy";
636 tx-fifo-resize;
637 snps,is-utmi-l1-suspend;
638 snps,hird-threshold = /bits/ 8 <0x0>;
644 intc: interrupt-controller@b000000 {
645 compatible = "qcom,msm-qgic2";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 interrupt-controller;
653 #interrupt-cells = <3>;
658 compatible = "arm,gic-v2m-frame";
660 msi-controller;
664 compatible = "arm,gic-v2m-frame";
666 msi-controller;
670 compatible = "arm,gic-v2m-frame";
672 msi-controller;
677 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
681 timeout-sec = <30>;
685 compatible = "qcom,ipq9574-apcs-apps-global",
686 "qcom,ipq6018-apcs-apps-global";
688 #clock-cells = <1>;
689 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
690 clock-names = "pll", "xo", "gpll0";
691 #mbox-cells = <1>;
695 compatible = "qcom,ipq9574-a73pll";
697 #clock-cells = <0>;
699 clock-names = "xo";
703 compatible = "arm,armv7-timer-mem";
705 #address-cells = <1>;
706 #size-cells = <1>;
712 frame-number = <0>;
719 frame-number = <1>;
726 frame-number = <2>;
733 frame-number = <3>;
740 frame-number = <4>;
747 frame-number = <5>;
754 frame-number = <6>;
761 thermal-zones {
762 nss-top-thermal {
763 thermal-sensors = <&tsens 3>;
766 nss-top-critical {
774 ubi-0-thermal {
775 thermal-sensors = <&tsens 4>;
778 ubi_0-critical {
786 ubi-1-thermal {
787 thermal-sensors = <&tsens 5>;
790 ubi_1-critical {
798 ubi-2-thermal {
799 thermal-sensors = <&tsens 6>;
802 ubi_2-critical {
810 ubi-3-thermal {
811 thermal-sensors = <&tsens 7>;
814 ubi_3-critical {
822 cpuss0-thermal {
823 thermal-sensors = <&tsens 8>;
826 cpu-critical {
834 cpuss1-thermal {
835 thermal-sensors = <&tsens 9>;
838 cpu-critical {
846 cpu0-thermal {
847 thermal-sensors = <&tsens 10>;
850 cpu0_crit: cpu-critical {
856 cpu0_alert: cpu-passive {
863 cooling-maps {
866 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
874 cpu1-thermal {
875 thermal-sensors = <&tsens 11>;
878 cpu1_crit: cpu-critical {
884 cpu1_alert: cpu-passive {
891 cooling-maps {
894 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
902 cpu2-thermal {
903 thermal-sensors = <&tsens 12>;
906 cpu2_crit: cpu-critical {
912 cpu2_alert: cpu-passive {
919 cooling-maps {
922 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
930 cpu3-thermal {
931 thermal-sensors = <&tsens 13>;
934 cpu3_crit: cpu-critical {
940 cpu3_alert: cpu-passive {
947 cooling-maps {
950 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
958 wcss-phyb-thermal {
959 thermal-sensors = <&tsens 14>;
962 wcss_phyb-critical {
970 top-glue-thermal {
971 thermal-sensors = <&tsens 15>;
974 top_glue-critical {
984 compatible = "arm,armv8-timer";