Lines Matching +full:0 +full:x02900000
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
142 ranges = <0x02900800 0x02900800 0x11800>;
148 reg = <0x2901000 0x100>;
162 reg = <0x2901100 0x100>;
176 reg = <0x2901200 0x100>;
190 reg = <0x2901300 0x100>;
204 reg = <0x2901400 0x100>;
218 reg = <0x2901500 0x100>;
232 reg = <0x2902000 0x200>;
240 reg = <0x2902200 0x200>;
248 reg = <0x2902400 0x200>;
256 reg = <0x2902600 0x200>;
264 reg = <0x2903000 0x100>;
272 reg = <0x2903100 0x100>;
280 reg = <0x2903200 0x100>;
288 reg = <0x2903300 0x100>;
296 reg = <0x2903800 0x100>;
304 reg = <0x2903900 0x100>;
312 reg = <0x2903a00 0x100>;
320 reg = <0x2903b00 0x100>;
327 reg = <0x2904000 0x100>;
339 reg = <0x2904100 0x100>;
351 reg = <0x2904200 0x100>;
363 reg = <0x2904300 0x100>;
375 reg = <0x2905000 0x100>;
387 reg = <0x2905100 0x100>;
400 reg = <0x2908000 0x100>;
410 reg = <0x2908100 0x100>;
416 reg = <0x2908200 0x200>;
423 reg = <0x290a000 0x200>;
431 reg = <0x290a200 0x200>;
439 reg = <0x290bb00 0x800>;
446 reg = <0x0290f000 0x1000>;
492 reg = <0x2910000 0x2000>;
500 reg = <0x02930000 0x20000>;
502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
545 reg = <0x02a41000 0x1000>,
546 <0x02a42000 0x2000>;
557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
558 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
559 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
560 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
561 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
562 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
571 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
581 reg = <0x0 0x02c60000 0x0 0x50000>;
586 #interconnect-cells = <0>;
594 reg = <0x0 0x03010000 0x0 0x000e0000>;
595 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
610 reg = <0x0 0x03100000 0x0 0x40>;
620 reg = <0x0 0x03110000 0x0 0x40>;
632 reg = <0x0 0x03130000 0x0 0x40>;
644 reg = <0x0 0x03140000 0x0 0x40>;
656 reg = <0x0 0x03150000 0x0 0x40>;
668 reg = <0x0 0x03160000 0x0 0x10000>;
671 #size-cells = <0>;
683 reg = <0x0 0x03180000 0x0 0x10000>;
686 #size-cells = <0>;
699 reg = <0x0 0x03190000 0x0 0x10000>;
702 #size-cells = <0>;
708 pinctrl-0 = <&state_dpaux1_i2c>;
718 reg = <0x0 0x031a0000 0x0 0x10000>;
721 #size-cells = <0>;
732 reg = <0x0 0x031b0000 0x0 0x10000>;
735 #size-cells = <0>;
741 pinctrl-0 = <&state_dpaux_i2c>;
750 reg = <0x0 0x031c0000 0x0 0x10000>;
753 #size-cells = <0>;
765 reg = <0x0 0x031e0000 0x0 0x10000>;
768 #size-cells = <0>;
780 reg = <0x0 0x3280000 0x0 0x10000>;
790 reg = <0x0 0x3290000 0x0 0x10000>;
800 reg = <0x0 0x32a0000 0x0 0x10000>;
810 reg = <0x0 0x32c0000 0x0 0x10000>;
820 reg = <0x0 0x32d0000 0x0 0x10000>;
830 reg = <0x0 0x32e0000 0x0 0x10000>;
840 reg = <0x0 0x32f0000 0x0 0x10000>;
850 reg = <0x0 0x03400000 0x0 0x10000>;
862 pinctrl-0 = <&sdmmc1_3v3>;
864 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
865 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
866 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
868 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
869 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
870 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>;
880 reg = <0x0 0x03420000 0x0 0x10000>;
892 pinctrl-0 = <&sdmmc2_3v3>;
894 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
895 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
896 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
898 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>;
905 reg = <0x0 0x03440000 0x0 0x10000>;
917 pinctrl-0 = <&sdmmc3_3v3>;
919 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
921 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
922 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
923 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
925 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>;
932 reg = <0x0 0x03460000 0x0 0x10000>;
946 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
947 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
948 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
950 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
952 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>;
962 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
963 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
964 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
990 reg = <0x0 0x03510000 0x0 0x10000>;
1010 reg = <0x0 0x03520000 0x0 0x1000>,
1011 <0x0 0x03540000 0x0 0x1000>;
1027 usb2-0 {
1029 #phy-cells = <0>;
1034 #phy-cells = <0>;
1039 #phy-cells = <0>;
1050 hsic-0 {
1052 #phy-cells = <0>;
1061 usb3-0 {
1063 #phy-cells = <0>;
1068 #phy-cells = <0>;
1073 #phy-cells = <0>;
1080 usb2-0 {
1092 hsic-0 {
1096 usb3-0 {
1112 reg = <0x0 0x03530000 0x0 0x8000>,
1113 <0x0 0x03538000 0x0 0x1000>;
1137 #size-cells = <0>;
1145 reg = <0x0 0x03550000 0x0 0x8000>,
1146 <0x0 0x03558000 0x0 0x1000>;
1167 reg = <0x0 0x03820000 0x0 0x10000>;
1176 reg = <0x0 0x03881000 0x0 0x1000>,
1177 <0x0 0x03882000 0x0 0x2000>,
1178 <0x0 0x03884000 0x0 0x2000>,
1179 <0x0 0x03886000 0x0 0x2000>;
1187 reg = <0x0 0x03960000 0x0 0x10000>;
1196 reg = <0x0 0x03c00000 0x0 0xa0000>;
1205 reg = <0x0 0x0c240000 0x0 0x10000>;
1208 #size-cells = <0>;
1220 reg = <0x0 0x0c250000 0x0 0x10000>;
1223 #size-cells = <0>;
1228 dmas = <&gpcdma 0>, <&gpcdma 0>;
1235 reg = <0x0 0x0c280000 0x0 0x40>;
1247 reg = <0x0 0x0c290000 0x0 0x40>;
1259 reg = <0 0x0c2a0000 0 0x10000>;
1270 reg = <0x0 0xc2f0000 0x0 0x1000>,
1271 <0x0 0xc2f1000 0x0 0x1000>;
1281 reg = <0x0 0xc340000 0x0 0x10000>;
1291 reg = <0 0x0c360000 0 0x10000>,
1292 <0 0x0c370000 0 0x10000>,
1293 <0 0x0c380000 0 0x10000>,
1294 <0 0x0c390000 0 0x10000>;
1333 reg = <0x0 0x0e000000 0x0 0x400000>;
1342 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1343 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1344 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1352 interrupt-map-mask = <0 0 0 0>;
1353 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1355 bus-range = <0x00 0xff>;
1359 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1360 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1361 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1362 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1363 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1364 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1381 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1382 iommu-map-mask = <0x0>;
1386 pci@1,0 {
1388 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1389 reg = <0x000800 0 0 0 0>;
1399 pci@2,0 {
1401 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1402 reg = <0x001000 0 0 0 0>;
1412 pci@3,0 {
1414 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1415 reg = <0x001800 0 0 0 0>;
1428 reg = <0 0x12000000 0 0x800000>;
1494 stream-match-mask = <0x7f80>;
1503 reg = <0x0 0x13e00000 0x0 0x10000>,
1504 <0x0 0x13e10000 0x0 0x10000>;
1517 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1525 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1536 reg = <0x15040000 0x10000>;
1564 #size-cells = <0>;
1570 reg = <0x15200000 0x00040000>;
1591 ranges = <0x15200000 0x15200000 0x40000>;
1595 reg = <0x15200000 0x10000>;
1609 nvidia,head = <0>;
1614 reg = <0x15210000 0x10000>;
1633 reg = <0x15220000 0x10000>;
1653 reg = <0x15300000 0x10000>;
1668 reg = <0x15340000 0x40000>;
1684 reg = <0x15380000 0x40000>;
1699 reg = <0x15400000 0x10000>;
1714 reg = <0x15480000 0x40000>;
1730 reg = <0x154c0000 0x40000>;
1745 reg = <0x15540000 0x10000>;
1757 pinctrl-0 = <&state_dpaux_aux>;
1764 nvidia,interface = <0>;
1769 reg = <0x15580000 0x10000>;
1781 pinctrl-0 = <&state_dpaux1_aux>;
1793 reg = <0x155c0000 0x10000>;
1821 #size-cells = <0>;
1827 reg = <0x15880000 0x10000>;
1835 reg = <0x15900000 0x10000>;
1850 reg = <0x15940000 0x10000>;
1866 reg = <0x0 0x17000000 0x0 0x1000000>,
1867 <0x0 0x18000000 0x0 0x1000000>;
1884 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1889 reg = <0x0 0x30000000 0x0 0x50000>;
1892 ranges = <0x0 0x0 0x30000000 0x50000>;
1896 reg = <0x4e000 0x1000>;
1902 reg = <0x4f000 0x1000>;
1927 #size-cells = <0>;
1939 #size-cells = <0>;
1941 denver_0: cpu@0 {
1944 i-cache-size = <0x20000>;
1947 d-cache-size = <0x10000>;
1951 reg = <0x000>;
1957 i-cache-size = <0x20000>;
1960 d-cache-size = <0x10000>;
1964 reg = <0x001>;
1970 i-cache-size = <0xC000>;
1973 d-cache-size = <0x8000>;
1977 reg = <0x100>;
1983 i-cache-size = <0xC000>;
1986 d-cache-size = <0x8000>;
1990 reg = <0x101>;
1996 i-cache-size = <0xC000>;
1999 d-cache-size = <0x8000>;
2003 reg = <0x102>;
2009 i-cache-size = <0xC000>;
2012 d-cache-size = <0x8000>;
2016 reg = <0x103>;
2023 cache-size = <0x200000>;
2032 cache-size = <0x200000>;
2063 assigned-clock-parents = <0>,
2079 polling-delay = <0>;
2087 hysteresis = <0>;
2098 polling-delay = <0>;
2106 hysteresis = <0>;
2116 polling-delay = <0>;
2124 hysteresis = <0>;
2134 polling-delay = <0>;
2142 hysteresis = <0>;
2152 polling-delay = <0>;
2160 hysteresis = <0>;