Lines Matching +full:0 +full:- +full:rtic +full:- +full:memory
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
24 rtic-b = &rtic_b;
25 rtic-c = &rtic_c;
26 rtic-d = &rtic_d;
27 sec-mon = &sec_mon;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
36 compatible = "arm,cortex-a53";
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39 #cooling-cells = <2>;
40 cpu-idle-states = <&CPU_PH20>;
44 idle-states {
46 * PSCI node is not added default, U-boot will add missing
49 entry-method = "psci";
51 CPU_PH20: cpu-ph20 {
52 compatible = "arm,idle-state";
53 idle-state-name = "PH20";
54 arm,psci-suspend-param = <0x0>;
55 entry-latency-us = <1000>;
56 exit-latency-us = <1000>;
57 min-residency-us = <3000>;
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <125000000>;
65 clock-output-names = "sysclk";
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <100000000>;
72 clock-output-names = "coreclk";
76 compatible = "arm,armv8-timer";
78 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
84 compatible = "arm,cortex-a53-pmu";
88 gic: interrupt-controller@1400000 {
89 compatible = "arm,gic-400";
90 #address-cells = <0>;
91 #interrupt-cells = <3>;
92 interrupt-controller;
93 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
94 <0x0 0x1402000 0 0x2000>, /* GICC */
95 <0x0 0x1404000 0 0x2000>, /* GICH */
96 <0x0 0x1406000 0 0x2000>; /* GICV */
101 compatible = "syscon-reboot";
103 offset = <0xb0>;
104 mask = <0x02>;
107 thermal-zones {
108 cpu_thermal: cpu-thermal {
109 polling-delay-passive = <1000>;
110 polling-delay = <5000>;
111 thermal-sensors = <&tmu 0>;
114 cpu_alert: cpu-alert {
120 cpu_crit: cpu-crit {
127 cooling-maps {
130 cooling-device =
139 compatible = "simple-bus";
140 #address-cells = <2>;
141 #size-cells = <2>;
145 compatible = "fsl,ls1021a-qspi";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 reg = <0x0 0x1550000 0x0 0x10000>,
149 <0x0 0x40000000 0x0 0x10000000>;
150 reg-names = "QuadSPI", "QuadSPI-memory";
152 clock-names = "qspi_en", "qspi";
161 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
162 reg = <0x0 0x1560000 0x0 0x10000>;
166 voltage-ranges = <1800 1800 3300 3300>;
167 sdhci,auto-cmd12;
168 bus-width = <4>;
173 compatible = "fsl,ls1012a-scfg", "syscon";
174 reg = <0x0 0x1570000 0x0 0x10000>;
175 big-endian;
179 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
180 reg = <0x0 0x1580000 0x0 0x10000>;
184 voltage-ranges = <1800 1800 3300 3300>;
185 sdhci,auto-cmd12;
186 broken-cd;
187 bus-width = <4>;
192 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
193 "fsl,sec-v4.0";
194 fsl,sec-era = <8>;
195 #address-cells = <1>;
196 #size-cells = <1>;
197 ranges = <0x0 0x00 0x1700000 0x100000>;
198 reg = <0x00 0x1700000 0x0 0x100000>;
200 dma-coherent;
203 compatible = "fsl,sec-v5.4-job-ring",
204 "fsl,sec-v5.0-job-ring",
205 "fsl,sec-v4.0-job-ring";
206 reg = <0x10000 0x10000>;
211 compatible = "fsl,sec-v5.4-job-ring",
212 "fsl,sec-v5.0-job-ring",
213 "fsl,sec-v4.0-job-ring";
214 reg = <0x20000 0x10000>;
219 compatible = "fsl,sec-v5.4-job-ring",
220 "fsl,sec-v5.0-job-ring",
221 "fsl,sec-v4.0-job-ring";
222 reg = <0x30000 0x10000>;
227 compatible = "fsl,sec-v5.4-job-ring",
228 "fsl,sec-v5.0-job-ring",
229 "fsl,sec-v4.0-job-ring";
230 reg = <0x40000 0x10000>;
234 rtic@60000 {
235 compatible = "fsl,sec-v5.4-rtic",
236 "fsl,sec-v5.0-rtic",
237 "fsl,sec-v4.0-rtic";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 reg = <0x60000 0x100>, <0x60e00 0x18>;
241 ranges = <0x0 0x60100 0x500>;
243 rtic_a: rtic-a@0 {
244 compatible = "fsl,sec-v5.4-rtic-memory",
245 "fsl,sec-v5.0-rtic-memory",
246 "fsl,sec-v4.0-rtic-memory";
247 reg = <0x00 0x20>, <0x100 0x100>;
250 rtic_b: rtic-b@20 {
251 compatible = "fsl,sec-v5.4-rtic-memory",
252 "fsl,sec-v5.0-rtic-memory",
253 "fsl,sec-v4.0-rtic-memory";
254 reg = <0x20 0x20>, <0x200 0x100>;
257 rtic_c: rtic-c@40 {
258 compatible = "fsl,sec-v5.4-rtic-memory",
259 "fsl,sec-v5.0-rtic-memory",
260 "fsl,sec-v4.0-rtic-memory";
261 reg = <0x40 0x20>, <0x300 0x100>;
264 rtic_d: rtic-d@60 {
265 compatible = "fsl,sec-v5.4-rtic-memory",
266 "fsl,sec-v5.0-rtic-memory",
267 "fsl,sec-v4.0-rtic-memory";
268 reg = <0x60 0x20>, <0x400 0x100>;
274 compatible = "fsl,ls1021a-sfp";
275 reg = <0x0 0x1e80000 0x0 0x10000>;
278 clock-names = "sfp";
282 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
283 "fsl,sec-v4.0-mon";
284 reg = <0x0 0x1e90000 0x0 0x10000>;
290 compatible = "fsl,ls1012a-dcfg",
292 reg = <0x0 0x1ee0000 0x0 0x1000>;
293 big-endian;
297 compatible = "fsl,ls1012a-clockgen";
298 reg = <0x0 0x1ee1000 0x0 0x1000>;
299 #clock-cells = <2>;
301 clock-names = "sysclk", "coreclk";
305 compatible = "fsl,qoriq-tmu";
306 reg = <0x0 0x1f00000 0x0 0x10000>;
308 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
309 fsl,tmu-calibration =
310 <0x00000000 0x00000025>,
311 <0x00000001 0x0000002c>,
312 <0x00000002 0x00000032>,
313 <0x00000003 0x00000039>,
314 <0x00000004 0x0000003f>,
315 <0x00000005 0x00000046>,
316 <0x00000006 0x0000004c>,
317 <0x00000007 0x00000053>,
318 <0x00000008 0x00000059>,
319 <0x00000009 0x0000005f>,
320 <0x0000000a 0x00000066>,
321 <0x0000000b 0x0000006c>,
323 <0x00010000 0x00000026>,
324 <0x00010001 0x0000002d>,
325 <0x00010002 0x00000035>,
326 <0x00010003 0x0000003d>,
327 <0x00010004 0x00000045>,
328 <0x00010005 0x0000004d>,
329 <0x00010006 0x00000055>,
330 <0x00010007 0x0000005d>,
331 <0x00010008 0x00000065>,
332 <0x00010009 0x0000006d>,
334 <0x00020000 0x00000026>,
335 <0x00020001 0x00000030>,
336 <0x00020002 0x0000003a>,
337 <0x00020003 0x00000044>,
338 <0x00020004 0x0000004e>,
339 <0x00020005 0x00000059>,
340 <0x00020006 0x00000063>,
342 <0x00030000 0x00000014>,
343 <0x00030001 0x00000021>,
344 <0x00030002 0x0000002e>,
345 <0x00030003 0x0000003a>,
346 <0x00030004 0x00000047>,
347 <0x00030005 0x00000053>,
348 <0x00030006 0x00000060>;
349 #thermal-sensor-cells = <1>;
353 compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 reg = <0x0 0x2180000 0x0 0x10000>;
360 scl-gpios = <&gpio0 2 0>;
365 compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c";
366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <0x0 0x2190000 0x0 0x10000>;
372 scl-gpios = <&gpio0 13 0>;
377 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 reg = <0x0 0x2100000 0x0 0x10000>;
382 clock-names = "dspi";
385 spi-num-chipselects = <5>;
386 big-endian;
392 reg = <0x00 0x21c0500 0x0 0x100>;
401 reg = <0x00 0x21c0600 0x0 0x100>;
409 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
410 reg = <0x0 0x2300000 0x0 0x10000>;
412 gpio-controller;
413 #gpio-cells = <2>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
419 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
420 reg = <0x0 0x2310000 0x0 0x10000>;
422 gpio-controller;
423 #gpio-cells = <2>;
424 interrupt-controller;
425 #interrupt-cells = <2>;
429 compatible = "fsl,ls1012a-wdt",
430 "fsl,imx21-wdt";
431 reg = <0x0 0x2ad0000 0x0 0x10000>;
434 big-endian;
438 #sound-dai-cells = <0>;
439 compatible = "fsl,vf610-sai";
440 reg = <0x0 0x2b50000 0x0 0x10000>;
450 clock-names = "bus", "mclk1", "mclk2", "mclk3";
451 dma-names = "rx", "tx";
458 #sound-dai-cells = <0>;
459 compatible = "fsl,vf610-sai";
460 reg = <0x0 0x2b60000 0x0 0x10000>;
470 clock-names = "bus", "mclk1", "mclk2", "mclk3";
471 dma-names = "rx", "tx";
477 edma0: dma-controller@2c00000 {
478 #dma-cells = <2>;
479 compatible = "fsl,vf610-edma";
480 reg = <0x0 0x2c00000 0x0 0x10000>,
481 <0x0 0x2c10000 0x0 0x10000>,
482 <0x0 0x2c20000 0x0 0x10000>;
485 interrupt-names = "edma-tx", "edma-err";
486 dma-channels = <32>;
487 big-endian;
488 clock-names = "dmamux0", "dmamux1";
496 compatible = "fsl,ls1012a-dwc3", "fsl,ls1028a-dwc3";
497 reg = <0x0 0x2f00000 0x0 0x10000>;
500 dma-coherent;
501 snps,quirk-frame-length-adjustment = <0x20>;
503 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
507 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
508 reg = <0x0 0x3200000 0x0 0x10000>,
509 <0x0 0x20140520 0x0 0x4>;
510 reg-names = "ahci", "sata-ecc";
514 dma-coherent;
519 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
520 reg = <0x0 0x8600000 0x0 0x1000>;
526 msi: msi-controller1@1572000 {
527 compatible = "fsl,ls1012a-msi";
528 reg = <0x0 0x1572000 0x0 0x8>;
529 msi-controller;
534 compatible = "fsl,ls1012a-pcie";
535 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
536 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
537 reg-names = "regs", "config";
540 interrupt-names = "pme", "aer";
541 #address-cells = <3>;
542 #size-cells = <2>;
544 bus-range = <0x0 0xff>;
545 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
546 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
547 msi-parent = <&msi>;
548 #interrupt-cells = <1>;
549 interrupt-map-mask = <0 0 0 7>;
550 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
551 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
552 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
553 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
554 big-endian;
558 rcpm: wakeup-controller@1ee2140 {
559 compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
560 reg = <0x0 0x1ee2140 0x0 0x4>;
561 #fsl,rcpm-wakeup-cells = <1>;
565 compatible = "fsl,ls1012a-ftm-alarm";
566 reg = <0x0 0x29d0000 0x0 0x10000>;
567 fsl,rcpm-wakeup = <&rcpm 0x20000>;
569 big-endian;
575 compatible = "linaro,optee-tz";