Lines Matching full:affected
445 The affected design reports FEAT_HAFDBS as not implemented in
478 the kernel if an affected CPU is detected.
500 the kernel if an affected CPU is detected.
523 only patch the kernel if an affected CPU is detected.
545 the kernel if an affected CPU is detected.
556 Affected Cortex-A57 parts might deadlock when exclusive load/store
563 the kernel if an affected CPU is detected.
574 Affected Cortex-A57 parts might report a Stage 2 translation
583 the kernel if an affected CPU is detected.
595 Affected parts may corrupt the AES state if an interrupt is
611 When running a compat (AArch32) userspace on an affected Cortex-A53
620 the kernel if an affected CPU is detected.
644 Affected Cortex-A55 cores (all revisions) could cause incorrect
647 of hardware DBM locally on the affected cores. CPUs not affected by
660 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
676 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
702 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
712 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
717 Under very rare circumstances, affected Cortex-A55 CPUs
722 Work around this by adding the affected CPUs to the list that needs
733 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
750 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
768 Affected Neoverse-N1 cores could execute a stale instruction when
783 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
805 Affected Cortex-A510 might not respect the ordering rules for
807 is to not enable the feature on affected CPUs.
816 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
833 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
849 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
867 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
887 Affected cores may fail to flush the trace data on a TSB instruction, when
891 Workaround is to issue two TSB consecutively on affected cores.
902 Affected cores may fail to flush the trace data on a TSB instruction, when
906 Workaround is to issue two TSB consecutively on affected cores.
921 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
939 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
950 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
955 Under very rare circumstances, affected Cortex-A510 CPUs
960 Work around this by adding the affected CPUs to the list that needs
972 Affected Cortex-A510 core might fail to write into system registers after the
978 is stopped and before performing a system register write to one of the affected
990 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1013 Affected Cortex-A510 core might cause trace data corruption, when being written
1018 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1032 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1035 Work around this problem by returning 0 when reading the affected counter in
1037 is the same to firmware disabling affected counters.
1067 On an affected Cortex-A520 core, a speculatively executed unprivileged
1081 On an affected Cortex-A510 core, a speculatively executed unprivileged
1114 On affected cores "MSR SSBS, #0" instructions may not affect