Lines Matching +full:0 +full:x10000000
15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
80 0x80000000 0x80000000 0x20000000
81 0xb0000000 0xb0000000 0x22000000
82 0xd8000000 0xd8000000 0x01000000
83 0xe0000000 0xe0000000 0x10000000>;
87 reg = <0xb3000000 0x100>;
88 interrupts = <0 28 0x4>;
94 reg = <0xb2800000 0x1000>;
95 interrupts = <0 29 0x4>;
97 dmas = <&dwdma0 0 0 0>;
103 reg = <0xea800000 0x1000>;
104 interrupts = <0 19 0x4>;
112 block_size = <0xfff>;
120 reg = <0xeb000000 0x1000>;
121 interrupts = <0 59 0x4>;
130 block_size = <0xfff>;
139 reg = <0xb0000000 0x1000 /* FSMC Register*/
140 0xb0800000 0x0010 /* NAND Base DATA */
141 0xb0820000 0x0010 /* NAND Base ADDR */
142 0xb0810000 0x0010>; /* NAND Base CMD */
144 interrupts = <0 20 0x4>,
145 <0 21 0x4>,
146 <0 22 0x4>,
147 <0 23 0x4>;
154 reg = <0xe2000000 0x8000>;
155 interrupts = <0 33 0x4>,
156 <0 34 0x4>;
163 #address-cells = <0>;
164 #size-cells = <0>;
172 reg = <0xea000000 0x1000>;
173 interrupts = <0 30 0x4>;
179 reg = <0xe4800000 0x1000>;
180 interrupts = <0 64 0x4>;
181 usbh0_id = <0>;
187 reg = <0xe5800000 0x1000>;
188 interrupts = <0 66 0x4>;
195 reg = <0xe4000000 0x1000>;
196 interrupts = <0 65 0x4>;
197 usbh0_id = <0>;
203 reg = <0xe5000000 0x1000>;
204 interrupts = <0 67 0x4>;
213 ranges = <0x50000000 0x50000000 0x10000000
214 0xb0000000 0xb0000000 0x10000000
215 0xd0000000 0xd0000000 0x02000000
216 0xd8000000 0xd8000000 0x01000000
217 0xe0000000 0xe0000000 0x10000000>;
221 reg = <0xe0700000 0x1000>;
226 reg = <0xe0600000 0x1000>;
227 interrupts = <0 24 0x4>;
237 reg = <0xe0680000 0x1000>;
238 interrupts = <0 25 0x4>;
248 reg = <0xe0300000 0x1000>;
249 interrupts = <0 52 0x4>;
255 #size-cells = <0>;
257 reg = <0xe0280000 0x1000>;
258 interrupts = <0 41 0x4>;
264 reg = <0xe0180000 0x1000>;
266 interrupts = <0 10 0x4>,
267 <0 11 0x4>;
273 reg = <0xe0200000 0x1000>;
275 interrupts = <0 26 0x4>,
276 <0 53 0x4>;
282 reg = <0xe0100000 0x1000>;
284 #size-cells = <0>;
285 interrupts = <0 31 0x4>;
287 dmas = <&dwdma0 5 0 0>,
288 <&dwdma0 4 0 0>;
294 reg = <0xe0580000 0x1000>;
295 interrupts = <0 36 0x4>;
301 reg = <0xe0000000 0x1000>;
302 interrupts = <0 35 0x4>;
308 reg = <0xe0080000 0x1000>;
309 interrupts = <0 12 0x4>;
315 reg = <0xe0380000 0x400>;
316 interrupts = <0 37 0x4>;
321 reg = <0xec800600 0x20>;
322 interrupts = <1 13 0x4>;
328 reg = <0xec800620 0x20>;
334 reg = <0xe07008c4 0x4>;
335 thermal_flags = <0x7000>;